mc68hc908gr8vp Freescale Semiconductor, Inc, mc68hc908gr8vp Datasheet - Page 107

• Manufacturer Part Number: mc68hc908gr8vp
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

10.7 Opcode Map
See
Freescale Semiconductor
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
SWI
TAP
TAX
TPA
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
TSX
TXA
TXS
WAIT
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
Source
Form
Table
Accumulator
Carry/borrow bit
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
10-2.
Subtract
Software Interrupt
Transfer A to CCR
Transfer A to X
Transfer CCR to A
Test for Negative or Zero
Transfer SP to H:X
Transfer X to A
Transfer H:X to SP
Enable Interrupts; Wait for Interrupt
Operation
Table 10-1. Instruction Set Summary (Sheet 6 of 6)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
(A) – $00 or (X) – $00 or (M) – $00
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
I bit ← 0; Inhibit CPU clocking
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; I ← 1
(SP) ← (H:X) – 1
H:X ← (SP) + 1
until interrupted
Description
A ← (A) – (M)
CCR ← (A)
A ← (CCR)
X ← (A)
A ← (X)
n
opr
PC
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
rr
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
SP
U
V
X
Z
&
|
⊕
( )
–( )
#
«
←
?
:
—
Relative program counter offset byte
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Negation (two’s complement)
Any bit
Operand (one or two bytes)
Program counter
Relative program counter offset byte
Stack pointer
Logical OR
Logical EXCLUSIVE OR
Contents of
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
V H I N Z C
– – 1 – – – INH
– – – – – – INH
– – – – – – INH
0 – –
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – 0 – – – INH
– –
on CCR
Effect
–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
INH
DIR
INH
INH
IX1
IX
SP1
9EE0
9ED0
9E6D
C0
D0
3D
4D
5D
6D
7D
A0
B0
E0
F0
83
84
97
85
95
9F
94
8F
Opcode Map
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
107
2
3
4
4
3
2
4
5
9
2
1
1
3
1
1
3
2
4
2
1
2
1