mc68hc908gr8vp Freescale Semiconductor, Inc, mc68hc908gr8vp Datasheet - Page 44

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mc68hc908gr8vp

Manufacturer Part Number
mc68hc908gr8vp
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Resets and Interrupts
4.2.3.1 Power-On Reset
A power-on reset is an internal reset caused by a positive transition on the V
go completely to 0 V to reset the MCU. This distinguishes between a reset and a POR. The POR is not a
brown-out detector, low-voltage detector, or glitch detector.
A power-on reset:
4.2.3.2 COP Reset
A COP reset is an internal reset caused by an overflow of the COP counter. A COP reset sets the COP
bit in the system integration module (SIM) reset status register.
To clear the COP counter and prevent a COP reset, write any value to the COP control register at location
$FFFF.
44
Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096
CGMXCLK cycles
Drives the RST pin low during the oscillator stabilization delay
Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay
Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator
stabilization delay
Sets the POR bit in the SIM reset status register and clears all other bits in the register
PORRST
1. PORRST is an internally generated power-on reset pulse.
CGMXCLK
INTERNAL
CGMOUT
RST PIN
RESET
OSC1
(1)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
Figure 4-1. Power-On Reset Recovery
CYCLES
4096
CYCLES
32
CYCLES
32
DD
pin. V
Freescale Semiconductor
DD
at the POR must

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