mc68hc908gr8vp Freescale Semiconductor, Inc, mc68hc908gr8vp Datasheet - Page 244

• Manufacturer Part Number: mc68hc908gr8vp
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module (TIM)
CHxMAX — Channel x Maximum Duty Cycle Bit
22.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
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When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As . CHxMAX Latency shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
Address:
Address:
The 100% PWM duty cycle is defined as a continuous high level if the PWM
polarity is 1 and a continuous low level if the PWM polarity is 0.
PTEx/TCHx
Reset:
Reset:
Read:
Read:
Write:
Write:
CHxMAX
OVERFLOW
T1CH0H, $0026 and T2CH0H, $0031
T1CH0L, $0027 and T2CH0L $0032
Bit 15
Bit 7
Bit 7
Bit 7
Figure 22-12. TIM Channel 0 Register High (TCH0H)
Figure 22-13. TIM Channel 0 Register Low (TCH0L)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
COMPARE
PERIOD
OUTPUT
14
6
6
6
Figure 22-11. CHxMAX Latency
OVERFLOW
13
5
5
5
COMPARE
OUTPUT
Indeterminate after reset
Indeterminate after reset
NOTE
OVERFLOW
12
4
4
4
COMPARE
OUTPUT
11
3
3
3
OVERFLOW
10
2
2
2
COMPARE
OUTPUT
1
9
1
1
OVERFLOW
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
Bit 0