mc68hc908lj24 Freescale Semiconductor, Inc, mc68hc908lj24 Datasheet - Page 259

• Manufacturer Part Number: mc68hc908lj24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

13.7.3.2 Character Reception
13.7.3.3 Data Sampling
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
RT CLOCK
RT CLOCK
SAMPLES
SCI_RxD
CLOCK
RESET
STATE
RT
Infrared Serial Communications Interface Module (IRSCI)
During an SCI reception, the receive shift register shifts characters in
from the RxD pin. The SCI data register (SCDR) is the read-only buffer
between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The SCI receiver full bit,
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the SCI receive interrupt enable bit, SCRIE,
in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt
request.
The receiver samples the RxD pin at the RT clock rate. The RT clock is
an internal signal with a frequency 16 times the baud rate. To adjust for
baud rate mismatch, the RT clock is resynchronized at the following
times (see
•
•
Figure 13-9. Receiver Data Sampling
QUALIFICATION
START BIT
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
Figure
13-9):
VERIFICATION
START BIT
Infrared Serial Communications Interface Module (IRSCI)
START BIT
SAMPLING
DATA
SCI Functional Description
LSB
Data Sheet
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