mc68hc908lj24 Freescale Semiconductor, Inc, mc68hc908lj24 Datasheet - Page 313

• Manufacturer Part Number: mc68hc908lj24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
SPMSTR — SPI Master Bit
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPWOM — SPI Wired-OR Mode Bit
SPE — SPI Enable
SPTIE— SPI Transmit Interrupt Enable
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
This read/write bit determines the logic state of the SPSCK pin
between transmissions. (See
transmit data between SPI modules, the SPI modules must have
identical CPOL values. Reset clears the CPOL bit.
This read/write bit controls the timing relationship between the serial
clock and SPI data. (See
data between SPI modules, the SPI modules must have identical
CPHA values. When CPHA = 0, the SS pin of the slave SPI module
must be set to logic 1 between bytes. (See
the CPHA bit.
This read/write bit disables the pullup devices on pins SPSCK, MOSI,
and MISO so that those pins become open-drain outputs.
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI. (See
the SPE bit.
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
1 = Master mode
0 = Slave mode
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
1 = SPI module enabled
0 = SPI module disabled
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
Serial Peripheral Interface Module (SPI)
Figure 14-4
14.10 Resetting the
Figure 14-4
Serial Peripheral Interface Module (SPI)
and
Figure
and
Figure
Figure
14-12.) Reset sets
SPI.) Reset clears
14-6.) To transmit
14-6.) To
I/O Registers
Data Sheet
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