mc68hc05pl4b Freescale Semiconductor, Inc, mc68hc05pl4b Datasheet
mc68hc05pl4b
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... Freescale Semiconductor 68HC05PL4B 68HC705PL4 68HC705PL4B © Freescale Semiconductor, Inc., 2004. All rights reserved. 68HC05PL4 SPECIFICATION (General Release) April 30, 1998 Consumer Systems Group Semiconductor Products Sector For More Information On This Product, Go to: www.freescale.com HC05PL4GRS/H REV 2.0 ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Section 1.1 FEATURES ...................................................................................................... 1-1 1.2 MCU BLOCK DIAGRAM .................................................................................. 1-2 1.3 PIN ASSIGNMENTS ........................................................................................ 1-3 1.4 PIN DESCRIPTIONS ....................................................................................... 1-4 1.4.1 VDD, VSS .................................................................................................... 1-4 1.4.2 OSC1, OSC2 ............................................................................................... 1-4 1.4.3 RESET......................................................................................................... 1-4 1.4.4 LED/IRQ ...................................................................................................... 1-4 1.4.5 PA0, PA1/DTMF, PA2/TCAP, PA3/TCMP, PA4-PA6 .................................. 1-5 1.4.6 PB0/KBI0-PB3/KBI3, PB4-PB7.................................................................... 1-5 1.4.7 PC0-PC7...................................................................................................... 1-6 2.1 MEMORY MAP ................................................................................................ 2-1 2.2 I/O REGISTERS .............................................................................................. 2-2 2.3 RAM ................................................................................................................. 2-2 2.4 ROM................................................................................................................. 2-2 2.5 COP WATCHDOG REGISTER (COPR).......................................................... 2-2 CENTRAL PROCESSING UNIT 3.1 REGISTERS .................................................................................................... 3-1 3.2 ACCUMULATOR (A) ....................................................................................... 3-2 3 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Section 4.4.2 Miscellaneous Control and Status Register................................................. 4-5 4.5 16-BIT TIMER INTERRUPTS .......................................................................... 4-6 4.5.1 Input Capture Interrupt................................................................................. 4-6 4.5.2 Output Compare Interrupt............................................................................ 4-6 4.5.3 Timer Overflow Interrupt .............................................................................. 4-6 4.6 8-BIT TIMER INTERRUPT .............................................................................. 4-6 4.7 KEYBOARD INTERRUPT ............................................................................... 4-7 5.1 POWER-ON RESET ........................................................................................ 5-1 5.2 EXTERNAL RESET ......................................................................................... 5-2 5.3 INTERNAL RESETS ........................................................................................ 5-2 5.3.1 Power-On Reset (POR) ............................................................................... 5-3 5.3.2 Computer Operating Properly (COP) Reset ................................................ 5-3 5 ...
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... Freescale Semiconductor, Inc. Section 7.4 PORT C ........................................................................................................... 7-3 7.5 SUMMARY OF PORT A AND PORT B SHARED PINS .................................. 7-3 8.1 SYSTEM CLOCK SOURCE AND FREQUENCY OPTION.............................. 8-1 16-BIT PROGRAMMABLE TIMER 9.1 TIMER REGISTERS (TMRH, TMRL)............................................................... 9-2 9.2 ALTERNATE COUNTER REGISTERS (ACRH, ACRL) .................................. 9-4 9.3 INPUT CAPTURE REGISTERS ...................................................................... 9-5 9.4 OUTPUT COMPARE REGISTERS ................................................................. 9-6 9.5 TIMER CONTROL REGISTER (TCR) ............................................................. 9-8 9.5.1 Miscellaneous Control and Status Register for Timer16 ............................. 9-9 9 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Section 12.1.7 Indexed, 16-Bit Offset ................................................................................ 12-3 12.1.8 Relative...................................................................................................... 12-3 12.1.9 Instruction Types ....................................................................................... 12-3 12.1.10 Register/Memory Instructions .................................................................... 12-4 12.1.11 Read-Modify-Write Instructions ................................................................. 12-5 12.1.12 Jump/Branch Instructions .......................................................................... 12-5 12.1.13 Bit Manipulation Instructions...................................................................... 12-7 12.1.14 Control Instructions.................................................................................... 12-7 12.1.15 Instruction Set Summary ........................................................................... 12-8 ELECTRICAL SPECIFICATIONS 13.1 MAXIMUM RATINGS..................................................................................... 13-1 13.2 OPERATING TEMPERATURE RANGE ........................................................ 13-1 13.3 THERMAL CHARACTERISTICS ................................................................... 13-1 13.4 SUPPLY CURRENT CHARACTERISTICS ................................................... 13-2 13.5 DC ELECTRICAL CHARACTERISTICS (4V)................................................ 13-3 13 ...
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... Freescale Semiconductor, Inc. Figure 1-1 MC68HC05PL4 Block Diagram ....................................................................... 1-2 1-2 MC68HC05PL4 Pin Assignment ...................................................................... 1-3 1-3 MC68HC05PL4B Pin Assignment ................................................................... 1-3 1-4 Oscillator Connections ..................................................................................... 1-4 1-5 Miscellaneous Control and Status Register (MICSR) ...................................... 1-5 2-1 MC68HC05PL4 Memory Map .......................................................................... 2-1 2-2 COP Watchdog Register (COPR) .................................................................... 2-2 2-3 I/O Registers $0000-$000F.............................................................................. 2-3 2-4 I/O Registers $0010-$001F.............................................................................. 2-4 3-1 MC68HC05 Programming Model ..................................................................... 3-1 4-1 Interrupt Stacking Order................................................................................... 4-2 4-2 Interrupt Flowchart ........................................................................................... 4-3 4-3 External Interrupt Logic ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Figure A-1 MC68HC705PL4B Memory Map .....................................................................A-2 A-2 EPROM Programming Sequence ....................................................................A-4 A-3 MC68HC705PL4 Pin Assignment ....................................................................A-5 A-4 MC68HC705PL4B Pin Assignment .................................................................A-5 vi For More Information On This Product, April 30, 1998 LIST OF FIGURES Title Go to: www.freescale.com Page MC68HC05PL4 REV 2.0 ...
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... Freescale Semiconductor, Inc. Table 1-1 MC68HC05PL4 and MC68HC05PL4B Differences ......................................... 1-1 4-1 Vector Address for Interrupts and Reset.......................................................... 4-1 5-1 Reset Characteristics ....................................................................................... 5-7 6-1 Operation Mode Condition After Reset ............................................................ 6-1 7-1 I/O Pin Functions ............................................................................................. 7-2 7-2 Port A and Port B Shared Pins ........................................................................ 7-3 8-1 System Clock Divider Select ............................................................................ 8-1 8-2 System Clock Source Select............................................................................ 8-1 9-1 Output Compare Initialization Example............................................................ 9-8 12-1 Register/Memory Instructions ........................................................................ 12-4 12-2 Read-Modify-Write Instructions ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table viii For More Information On This Product, April 30, 1998 LIST OF TABLES Title Go to: www.freescale.com Page MC68HC05PL4 REV 2.0 ...
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... RAM • 4k-bytes of user ROM • ROM security • 23 (22 for MC68HC05PL4B) bidirectional I/O lines with: – 4 keyboard interrupts with pull-up resistor – 6 high current sink pins • Open-drain output for LED drive • Multiplexed DTMF output with built-in 6-bit D/A • ...
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... VSS † Available on MC68HC05PL4 only. †† Available on MC68HC05PL4B only. Figure 1-1. MC68HC05PL4 Block Diagram A line over a signal name indicates an active low signal. Any reference to voltage, current, or frequency speci ed in the following sections will refer to the nominal values. The exact values and their tolerance or limits are speci ed in Electr ical Speci cations section ...
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... Freescale Semiconductor, Inc. 1.3 PIN ASSIGNMENTS PB3/KBI3 PB2/KBI2 PB1/KBI1 Figure 1-2. MC68HC05PL4 Pin Assignment PB3/KBI3 PB2/KBI2 PB1/KBI1 Figure 1-3. MC68HC05PL4B Pin Assignment MC68HC05PL4 REV 2.0 For More Information On This Product, April 30, 1998 GENERAL RELEASE SPECIFICATION 28 OSC1 VSS 1 27 VDD PA0 2 26 PC7 PC0 3 25 PC1 ...
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... Power is supplied to the MCU using these pins. VDD is the positive supply and VSS is the ground pin. 1.4.2 OSC1, OSC2 OSC2 is only available on MC68HC05PL4B. The OSC1 and OSC2 pins are the connections for the on-chip oscillator — the following con gur ations are available: 1 ...
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... Freescale Semiconductor, Inc. triggering, the LED/IRQ pin requires an external resistor to VDD for “wired-OR” operation. If the LED/IRQ is not used, it must be tied to the VDD supply. The contains an internal Schmitt trigger as part of its input to improve noise immunity. When this pin is LED, the LED bit in the MISCR controls the on/off function of the connected LED ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1.4.7 PC0-PC7 These eight I/O lines comprise port C, a general purpose bidirectional I/O port. The state of any pin is software programmable and all port C lines are con gured as inputs during power-on or reset. PC4-PC7 have high current sinking capability; see Electrical Speci cations sec- tion for values ...
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... Freescale Semiconductor, Inc. This section describes the organization of the memory on the MC68HC05PL4. 2.1 MEMORY MAP The CPU can address 8k-bytes of memory space as shown in Figure 2-1 . The ROM portion of the memory holds the program instructions, xed data, user de ned v ectors, and interrupt service routines. The RAM portion of memory holds variable data ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 2.2 I/O REGISTERS The rst 32 addresses of the memor y space, $0000-$001F, are the I/O section. One I/O register is located outside the 32-byte I/O section, which is the Computer Operating Properly (COP) register mapped at $1FF0. The bit assignment of each I/O register is described in the respective sections and summarized in Figure 2-3 and Figure 2-4 ...
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... Freescale Semiconductor, Inc. ADDR REGISTER ACCESS Port A Data R $0000 PORTA W Port B Data R $0001 PORTB W Port C Data R $0002 PORTC W R $0003 RESERVED W R $0004 RESERVED W Port A Data Direction R $0005 DDRA W Port B Data Direction R $0006 DDRB W Port C Data Direction R $0007 DDRC W R $0008 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION ADDR REGISTER ACCESS R $0010 RESERVED W R $0011 RESERVED W Timer Control R $0012 TCR W Timer Status R $0013 TSR W Input Capture High R $0014 ICRH W Input Capture Low R $0015 ICRL W Output Compare High R $0016 OCRH W Output Compare Low R $0017 ...
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... Freescale Semiconductor, Inc. CENTRAL PROCESSING UNIT The MC68HC05PL4 has an 8k-bytes memory map. The stack has only 64 bytes. Therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00C0 and then wrap-around to $00FF. All other instructions and registers behave as described in this chapter. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 3.2 ACCUMULATOR (A) The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The CPU uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. The accumulator is not affected by a reset of the device. 3.3 INDEX REGISTER (X) The index register shown in Figure 3 8-bit register that can perform two functions: • ...
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... Freescale Semiconductor, Inc. Normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.6 CONDITION CODE REGISTER (CCR) The CCR shown in Figure 3 5-bit register in which four bits are used to indicate the results of the instruction just executed ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 3.6.5 Carry/Borrow Bit (C-Bit) The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates ...
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... Freescale Semiconductor, Inc. The CPU can be interrupted by ve different sources – one software and four hardware: • Non-maskable Software Interrupt Instruction (SWI) • External Asynchronous Interrupt (IRQ) • 16-Bit Timer • 8-Bit Timer • Keyboard Interrupt 4.1 INTERRUPT VECTORS Table 4-1 summarizes the reset and interrupt sources and vector assignments Table 4-1 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION If more than one interrupt request is pending, the CPU fetches the vector of the higher priority interrupt rst. A higher priority interrupt does not actually interrupt a lower priority interrupt service routine unless the lower priority interrupt service routine clears the I bit. ...
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... Freescale Semiconductor, Inc. FROM RESET YES I BIT SET? NO EXTERNAL INTERRUPT? 16-BIT TIMER INTERRUPT? 8-BIT TIMER INTERRUPT? KEYBOARD INTERRUPT? FETCH NEXT INSTRUCTION. SWI INSTRUCTION? RTI INSTRUCTION? Figure 4-2. Interrupt Flowchart MC68HC05PL4 REV 2.0 For More Information On This Product, April 30, 1998 GENERAL RELEASE SPECIFICATION YES CLEAR IRQ LATCH ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 4.3 SOFTWARE INTERRUPT The software interrupt (SWI) instruction causes a non-maskable interrupt. 4.4 EXTERNAL INTERRUPT The LED/IRQ pin is the source that generates external interrupt. Setting the I bit in the condition code register or clearing the IRQEN bit in the miscellaneous control/ status register disables this external interrupt ...
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... Freescale Semiconductor, Inc. IRQS LED/IRQ PH2 LED IRQEN Figure 4-3. External Interrupt Logic 4.4.2 Miscellaneous Control and Status Register BIT 7 BIT 6 MICSR R IRQEN IRQS $001C W RESET 0 Figure 4-4. Miscellaneous Control and Status Register (MICSR) IRQEN — External Interrupt Request Enable This read/write bit enables external interrupts. Reset clears the IRQEN bit. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 4.5 16-BIT TIMER INTERRUPTS The 16-bit programmable Timer can generate an interrupt whenever the following events occur: • Input capture • Output compare • Timer counter over o w Setting the I bit in the condition code register disables Timer interrupts. The con- trols for these interrupts are in the Timer control register (TCR) located at $0012 and in the status bits are in the Timer status register (TSR) located at $0013 ...
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... Freescale Semiconductor, Inc. 4.7 KEYBOARD INTERRUPT Port B has internal pull-up resistors (typically 100K ) and are enabled individually by setting the corresponding bit in the Pull-Up Enable Register (PUER). BIT 7 BIT 6 PUER R PUL7 PUL6 $000A W RESET 0 Figure 4-5. Pull-Up Enable Register (PUER) PB0 to PB3 have keyboard interrupt functions, with individual enable and ag bits in registers $000B and $000C ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 4-8 For More Information On This Product, April 30, 1998 INTERRUPTS Go to: www.freescale.com MC68HC05PL4 REV 2.0 ...
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... Freescale Semiconductor, Inc. This section describes the four reset sources and how they initialize the MCU. A reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user de ned reset v ec- tor address. The following conditions produce a reset: • ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION A 4064 t (internal clock cycle) delay after the oscillator becomes active allows CYC the clock generator to stabilize. If the RESET pin is at logic zero at the end of the multiple t time, the MCU remains in the reset condition until the signal on the CYC RESET pin goes to a logic one ...
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... Freescale Semiconductor, Inc. 5.3.1 Power-On Reset (POR) The internal POR is generated on power-up to allow the clock oscillator to stabi- lize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of 4064 internal processor bus clock cycles after the oscillator becomes active ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Use the following formula to calculate the COP time-out period: COP Time-out Period = (prescaler x 256 x 8) The clock input to the watchdog system is derived from the output of the Timer8, therefore a reset or preset of Timer8 may affect the COP watchdog time-out period ...
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... Freescale Semiconductor, Inc. 5.4 RESET STATES OF SUBSYSTEM IN MCU The following paragraphs describe how a reset initializes various sub-systems. 5.4.1 CPU A reset has the following effects on the CPU: • Loads the stack pointer with $FF. • Sets the I bit in the condition code register, inhibiting interrupts. • ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION • Does not affect the input capture edge bit (IEDG) in the TCR. • Does not affect the interrupt ags in the timer status register (TSR). • Does not affect the input capture registers (ICRH, ICRL). • ...
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... Freescale Semiconductor, Inc. 5.5 RESET CHARACTERISTICS Table 5-1. Reset Characteristics Characteristic 2 POR Recovery Voltage 2 POR V Slew Rate DD 2 Rising 2 Falling RESET Pulse Width (when bus clock active) RESET Pulldown Pulse Width (from internal reset) Note: 1. +2 design, not tested. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Internal 1 Reset RESET Pin Internal 3 Clock Internal ...
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... Freescale Semiconductor, Inc. This section describes the various operating modes of the MC68HC05PL4. 6.1 OPERATING MODES The MC68HC05PL4 has two operating modes: Single-Chip (Normal) Mode and Self-Check Mode. At the rising edge of the RESET, the device latches the states of LED/IRQ and PB0/KBI0 pins and places itself in the speci ed mode . RESET must be held low ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 6.2 LOW POWER MODES In each of its con gur ation modes the MC68HC05PL4 is capable of running in one of two low-power operating modes. The WAIT and STOP instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the oscillator ...
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... Freescale Semiconductor, Inc. STOP Stop External Oscillator, Stop Internal Timer Clock, Reset Start-up Delay Stop Internal Processor Clock, Clear I-Bit in CCR, and set IRQEN in MICSR Y External RESET? N IRQ Y External Interrupt? N Keyboard Y Interrupt? N Restart External Oscillator, start Stabilization Delay End of Stabilization Delay ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 6-4 For More Information On This Product, April 30, 1998 OPERATING MODES Go to: www.freescale.com MC68HC05PL4 REV 2.0 ...
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... In the MC68HC05PL4, 23 bidirectional I/O lines are available, arranged as one 7-bit I/O port (Port A), one 8-bit I/O port (Port B), and one 8-bit I/O port (Port C). In the MC68HC05PL4B, 22 bidirectional I/O lines are available, arranged as one 6-bit I/O port (Port A), one 8-bit I/O port (Port B), and one 8-bit I/O port (Port C). ...
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... Port pins PA5 and PA6 are high current sink pins; see Electrical Speci cations section f or values. Pin PA0 is only available on MC68HC05PL4. OSC2 replaces PA0 on MC68HC05PL4B. Pin PA1 becomes the DTMF output from the DAC when the DACEN bit is set in the DAC Control and Data Register ($000F). ...
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... Port B PB3-PB0 PUL3-PUL0 MC68HC05PL4 REV 2.0 For More Information On This Product, April 30, 1998 GENERAL RELEASE SPECIFICATION Pin Name PA0 or OSC2 OSC2 on MC68HC05PL4B PA1/DTMF PA2/TCAP 16-bit Timer Input Capture PA3/TCMP 16-bit Timer Output Compare PB3/KBI3-PB0/KBI0 INPUT/OUTPUT PORTS Go to: www.freescale.com Shared Functions PA0 on MC68HC05PL4 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 7-4 For More Information On This Product, April 30, 1998 INPUT/OUTPUT PORTS Go to: www.freescale.com MC68HC05PL4 REV 2.0 ...
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... Freescale Semiconductor, Inc. This section describes the system clock options for the MC68HC05PL4. 8.1 SYSTEM CLOCK SOURCE AND FREQUENCY OPTION The operating bus frequency of the MCU is dependent on the clock source (OSC1 or internal RC) and the clock divider ratio. These are selected in the System Clock Control Register (SYSCR) ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION FMODE — Fast Mode RC select FMODE selects the oscillating frequency of the internal RC. After power-on- reset, the default setting is 500kHz Internal RC oscillates at 500kHz 0 = Internal RC oscillates at 20kHz OSCF — OSC running Flag This bit is set when the external clock (External/crystal) from OSC1 is on. ...
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... Freescale Semiconductor, Inc. 16-BIT PROGRAMMABLE TIMER The MC68HC05PL4 MCU contains a 16-bit programmable Timer with an Input Capture function and an Output Compare function as shown by the block diagram in Figure 9-1. EDGE PA2 SELECT TCAP & DETECT LOGIC RESET TIMER CONTROL REGISTER $0012 INTERNAL DATA BUS Figure 9-1 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION The basis of the capture/compare Timer is a 16-bit free-running counter which increases in count with each internal bus clock cycle. The counter is the timing ref- erence for the input capture and output compare functions. The input capture and ...
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... Freescale Semiconductor, Inc. The timer registers (TMRH, TMRL) shown in Figure 9-3 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the timer registers has no effect. Reset of the device presets the timer counter to $FFFC. BIT 7 BIT 6 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 9.2 ALTERNATE COUNTER REGISTERS (ACRH, ACRL) The functional block diagram of the 16-bit free-running timer counter and alternate counter registers is shown in Figure 9-4. The alternate counter registers behave the same as the timer registers, except that any reads of the alternate counter will not have any effect on the TOF ag bit and Timer interrupts ...
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... Freescale Semiconductor, Inc. To prevent interrupts from occurring between readings of the ACRH and ACRL, set the I bit in the condition code register (CCR) before reading ACRH and clear the I bit after reading ACRL. 9.3 INPUT CAPTURE REGISTERS The input capture function is a technique whereby an external signal (connected to PA2/TCAP pin) is used to trigger the 16-bit timer counter ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION The result obtained by an input capture will be one count higher than the value of the free-running timer counter preceding the external transition. This delay is required for internal synchronization. Resolution is affected by the prescaler, allowing the free-running timer counter to increment once every four internal clock cycles (eight oscillator clock cycles) ...
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... Freescale Semiconductor, Inc. The planned action on the TCMP depends on the value stored in the OLVL bit in the TCR, and it occurs when the value of the 16-bit free-running timer counter matches the value in the output compare registers shown in Figure 9-3. These registers are read/write bits and are unaffected by reset. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 3. Read the TSR to arm the OCF for clearing. 4. Enable the output compare registers by writing to the OCRL. This also clears the OCF ag bit in the TSR. 5. Enable interrupts by clearing the I bit in the condition code register. A software example of this procedure is shown in Table 9-1. ...
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... Freescale Semiconductor, Inc. OCIE - OUTPUT COMPARE INTERRUPT ENABLE This read/write bit enables interrupts caused by an active signal on the TCMP pin. Reset clears the OCIE bit Output compare interrupts enabled Output compare interrupts disabled. TOIE - TIMER OVERFLOW INTERRUPT ENABLE This read/write bit enables interrupts caused by a timer over o w. Reset clears the TOIE bit ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION TCMPEN - TIMER OUTPUT COMPARE ENABLE The bit con gures por t pin PA3 for Timer16 output compare function (TCMP). At power-on-reset, this bit is cleared, PA3 is a standard I/O port pin, TCMP sig- nal to PA3 is disabled from Timer16. ...
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... Freescale Semiconductor, Inc. 9.7 16-BIT TIMER OPERATION DURING WAIT MODE During WAIT mode the 16-bit timer continues to operate normally and may gener- ate an interrupt to trigger the MCU out of the WAIT mode. 9.8 16-BIT TIMER OPERATION DURING STOP MODE When the MCU enters the STOP mode the free-running counter stops counting (the internal processor clock is stopped) ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 9-12 For More Information On This Product, April 30, 1998 16-BIT PROGRAMMABLE TIMER Go to: www.freescale.com MC68HC05PL4 REV 2.0 ...
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... Freescale Semiconductor, Inc. This section describes the 8-bit count down timer module. 10.1 OVERVIEW To COP Watchdog Circuit Internal Bus Clock 8 Figure 10-1. Timer8 Block Diagram As shown in Figure 10-1 this timer contains a single 8-bit software programmable countdown timer counter with a 3-bit software control prescaler. The counter’s value may be preset under software control and counts down to zero ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION The counter continues to count after it reaches zero, allowing the software to determine the number of internal or external clocks since the timer interrupt request bit (T8IF) was set. The counter may be read at any time by the processor without disturbing the count. The contents of the counter become stable prior to the read portion of a cycle and do not change during the read. The timer interrupt request bit (T8IF) remains set until cleared by writing a “ ...
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... Freescale Semiconductor, Inc. T8EN - Timer8 Enable This read/write bit enables the Timer8. Reset clears this bit Timer8 enabled 0 = Timer8 disabled PS2-PS0 - Prescaler select These read/write bits is used to select the clock frequency to drive the 8-bit timer counter. The counter will be driven by a internal bus clock (E-clock) through this prescaler ratio ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.5 8-BIT TIMER OPERATION DURING WAIT MODE The CPU clock halts during the WAIT mode, but the timer remains active. If the interrupts are enabled, the timer interrupt will cause the processor to exit the WAIT mode. 10.6 8-BIT TIMER OPERATION DURING STOP MODE The timer ceases counting in STOP mode ...
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... Freescale Semiconductor, Inc. DIGITAL TO ANALOG CONVERTER This section describes Digital-to-Analog module used for DTMF generation. 11.1 DAC CONTROL AND DATA REGISTER BIT 7 BIT 6 DACDR R DACEN $000F W reset: 0 Figure 11-1. DAC Control and Data Register DACEN - DAC Channel Enable Ths read/write bit enables/disables the DAC module for DTMF output. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 11.4 DAC CHARACTERISTICS (V = 4.0V 10 Characteristic Resolution Absolute Accuracy 4.0V 2.0V DAC Output Resistance DIGITAL TO ANALOG CONVERTER 11-2 For More Information On This Product, April 30, 1998 = unless otherwise noted Symbol — V out V out R dac Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. This section describes the addressing modes and instruction types. 12.1 ADDRESSING MODES The CPU uses eight addressing modes for addressing modes de ne the manner in which the CPU nds the data required to execute an instruction. The eight addressing modes are the following: • ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.1.3 Direct Direct instructions can access any of the rst 256 memor y addresses with two bytes. The rst b yte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address ...
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... Freescale Semiconductor, Inc. 12.1.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the conditional address of the operand. The rst byte after the opcode is the high byte of the 16-bit offset ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.1.10 Register/Memory Instructions Most of these instructions use two operands. One operand is in either the accumulator or the index register. The CPU nds the other oper and in memory. Table 12-1 lists the register/memory instructions. Table 12-1. Register/Memory Instructions Add Memory Byte and Carry Bit to Accumulator ...
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... Freescale Semiconductor, Inc. 12.1.11 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modi ed v alue back to the memory location or to the register. The test for negative or zero instruction (TST exception to the read-modify-write sequence because it does not write a replacement value. Table 12-2 lists the read-modify-write instructions ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION third byte to the program counter if the speci ed bit tests tr ue. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. ...
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... Freescale Semiconductor, Inc. 12.1.13 Bit Manipulation Instructions The CPU can set or clear any writable bit in the rst 256 b ytes of memory. Port registers, port data direction registers, timer registers, and on-chip RAM locations are in the rst 256 b ytes of memory. The CPU can also test and branch based on the state of any bit in any of the rst 256 memory locations ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.1.15 Instruction Set Summary Table 12 alphabetical list of all M68HC05 instructions and shows the effect of each instruction on the condition code register. Table 12-6. Instruction Set Summary Source Operation Form ADC # opr ADC opr ADC opr Add with Carry ...
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... Freescale Semiconductor, Inc. Table 12-6. Instruction Set Summary (Continued) Source Operation Form Branch if Half-Carry BHCS rel Bit Set BHI rel Branch if Higher Branch if Higher or BHS rel Same Branch if IRQ Pin BIH rel High Branch if IRQ Pin BIL rel Low BIT # opr BIT opr ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-6. Instruction Set Summary (Continued) Source Operation Form BSET n opr Set Bit n Branch to BSR rel Subroutine CLC Clear Carry Bit CLI Clear Interrupt Mask CLR opr CLRA CLRX Clear Byte CLR opr ,X CLR ,X CMP # opr ...
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... Freescale Semiconductor, Inc. Table 12-6. Instruction Set Summary (Continued) Source Operation Form INC opr INCA INCX Increment Byte INC opr ,X INC ,X JMP opr JMP opr JMP opr ,X Unconditional Jump JMP opr ,X JMP ,X JSR opr JSR opr JSR opr ,X Jump to Subroutine JSR opr ,X ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 12-6. Instruction Set Summary (Continued) Source Operation Form ORA # opr ORA opr Logical OR ORA opr Accumulator with ORA opr ,X Memory ORA opr ,X ORA ,X ROL opr ROLA Rotate Byte Left ROLX through Carry Bit ROL opr ,X ...
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... Freescale Semiconductor, Inc. Table 12-6. Instruction Set Summary (Continued) Source Operation Form SUB # opr SUB opr Subtract Memory SUB opr Byte from SUB opr ,X Accumulator SUB opr ,X SUB ,X SWI Software Interrupt Transfer TAX Accumulator to Index Register TST opr TSTA Test Memory Byte ...
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... Freescale Semiconductor, Inc. 12-14 For More Information On This Product, INSTRUCTION SET Go to: www.freescale.com MC68HC05PL4 REV 2.0 ...
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... Freescale Semiconductor, Inc. ELECTRICAL SPECIFICATIONS This section contains the electrical and timing speci cations f or the MC68HC05PL4. 13.1 MAXIMUM RATINGS Maximum ratings are the extreme limits the device can be exposed to without causing permanent damage to the chip. The device is not intended to operate at these conditions. The MCU contains circuitry that protects the inputs against dam- age from high static voltages ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13.4 SUPPLY CURRENT CHARACTERISTICS Characteristic V = 4 Internal RC (about 500kHz) Run Wait Stop External Crystal/Ceramic Resonator @ 5.12MHz Run Wait Stop V = 2 Internal RC (about 500kHz) Run Wait Stop External Crystal/Ceramic Resonator @ 2MHz Run Wait Stop NOTES: 1 ...
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... Freescale Semiconductor, Inc. 13.5 DC ELECTRICAL CHARACTERISTICS (4V) Characteristic Output Voltage load I = –10 A load Output High Voltage (I = –0.8 mA) load PA0:6, PB0:7, PC0:7, PD0:3, RESET Output Low Voltage (I = 1.6 mA) PA0:6, PB0:7, PC0:7, PD0:3, RESET load ( mA) LED/IRQ/V load PP High Sink Current (V = 0.4) OL Sink current per pin, PA5, PA6 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13.6 DC ELECTRICAL CHARACTERISTICS (2V) Characteristic Output Voltage load I = –10 A load Output High Voltage (I = –0.8 mA) load PA0:6, PB0:7, PC0:7, PD0:3, RESET Output Low Voltage (I = 1.6 mA) PA0:6, PB0:7, PC0:7, PD0:3, RESET load ( mA) LED/IRQ/V load PP High Sink Current ( ...
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... Freescale Semiconductor, Inc. 13.7 CONTROL TIMING (4V) Characteristic Frequency of Oscillation (OSC) RC Oscillator Option Crystal Oscillator Option External Clock Source Internal Operating Frequency, Crystal or External Clock (f RC Oscillator Option Crystal Oscillator Option External Clock Source Cycle Time RC Oscillator Option External oscillator or clock source OSC1 Pulse Width (external clock input) ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 13-6 For More Information On This Product, April 30, 1998 ELECTRICAL SPECIFICATIONS Go to: www.freescale.com MC68HC05PL4 REV 2.0 ...
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... Freescale Semiconductor, Inc. MECHANICAL SPECIFICATIONS This section provides the mechanical dimensions for the 28-pin PDIP, 28-pin SOIC, and 28-pin SSOP packages. 14.1 28-PIN PDIP (CASE 710 14.2 28-PIN SOIC (CASE 751F) - 28X 0.010 (0.25 -T- G 26X MC68HC05PL4 REV 2 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 14.3 28-PIN SSOP 1. 1. TOP VIEW + 0. - SIDE VIEW 0.235 MIN 0 MIN. PARTING LINE DETAIL 'A' NOTES: 1. MAXIMUM DIE THICKNESS ALLOWABLE IS 0.43mm (.017 INCHES). 2. DIMENSIONING & TOLERANCES PER ANSI.Y14.5M-1982. ...
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... Freescale Semiconductor, Inc. This appendix describes the MC68HC705PL4 and MC68HC705PL4B, the emula- tion parts for MC68HC05PL4 and MC68HC05PL4B respectively. The entire MC68HC05PL4 data MC68HC705PL4B, with exceptions outlined in this appendix. References to MC68HC705PL4 MC68HC705PL4 and MC68HC705PL4B devices, unless otherwise stated. A.1 INTRODUCTION The MC68HC705PL4 is an EPROM version of the MC68HC705PL4, and the MC68HC705PL4B is an EPROM version of the MC68HC705PL4B ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION $0000 I/O REGISTERS 32 BYTES $001F $0020 USER RAM 256 BYTES $00C0 STACK $00FF 64 BYTES $011F $0120 UNUSED $0DFF $0E00 USER EPROM 4096 BYTES $1DFF $1E00 BOOTSTRAP ROM 496 BYTES $1FEF $1FF0 USER VECTORS 16 BYTES $1FFF Figure A-1. MC68HC705PL4B Memory Map A ...
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... Freescale Semiconductor, Inc. PGM – EPROM ProGraM command 0 = Programming power is switched OFF from EPROM array Programming power is switched ON to EPROM array. If ELAT then PGM = 0. A.4.2 Programming Sequence The EPROM programming sequence is: 1. Set the ELAT bit 2. Write the data to the address to be programmed 3 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Figure A-2. EPROM Programming Sequence A-4 For More Information On This Product, April 30, 1998 START ELAT=1 Write EPROM byte EPGM=1 Wait 1ms EPGM=0 ELAT=0 Write Y additional byte? N END Go to: www.freescale.com MC68HC05PL4 REV 2.0 ...
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... Freescale Semiconductor, Inc. Figure A-3. MC68HC705PL4 Pin Assignment Figure A-4. MC68HC705PL4B Pin Assignment MC68HC05PL4 REV 2.0 For More Information On This Product, April 30, 1998 GENERAL RELEASE SPECIFICATION 28 VSS OSC1 1 27 VDD PA0 2 26 PC0 PC7 3 25 PC1 PC6 4 RESET 24 PA1/DTMF 5 23 PB7 PA2/TCAP 6 22 PA3/TCMP ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION A.6 SUPPLY CURRENT CHARACTERISTICS Characteristic 3.6V DD Internal RC (about 500kHz) Run Wait Stop External Crystal/Ceramic Resonator @ 5.12MHz Run Wait Stop NOTES indicated All values shown re ect a verage measurements. 3. Typical values at midpoint of voltage range only. ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center ...