mc68hc05pl4b Freescale Semiconductor, Inc, mc68hc05pl4b Datasheet - Page 37

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mc68hc05pl4b

Manufacturer Part Number
mc68hc05pl4b
Description
Low-cost Single-chip Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
5.4
5.4.1 CPU
5.4.2 I/O Registers
5.4.3 8-Bit Timer
5.4.4 16-Bit Programmable Timer
MC68HC05PL4
REV 2.0
RESET STATES OF SUBSYSTEM IN MCU
The following paragraphs describe how a reset initializes various sub-systems.
A reset has the following effects on the CPU:
A reset has the following effects on I/O registers:
A reset has the following effects on the 8-Bit Timer:
Therefore disables the timer 8 interrupt and preset the counter for POR cycle
delay.
A reset has the following effects on the 16-bit programmable Timer:
Loads the stack pointer with $FF.
Sets the I bit in the condition code register, inhibiting interrupts.
Loads the program counter with the user de ned reset vector from
locations $1FFE and $1FFF.
Clears the stop latch, enabling the CPU clock.
Clears the wait latch, bringing the CPU out of the wait mode.
Clears bits in data direction registers con gur ing pins as inputs:
– DDRA6–DDRA0 in DDRA for port A.
– DDRB7–DDRB0 in DDRB for port B.
– DDRC7–DDRC0 in DDRC for port C.
Has no effect on port A, B, C data registers.
Timer 8 system disabled (T8EN bit cleared)
Timer 8 interrupt request disabled
Timer 8 Pre-scalar preset to divide the internal bus clock by ratio 16
Timer 8 Counter register preset to $FF
Initializes the timer counter registers (TMRH, TMRL) to a value of
$FFFC.
Initializes the alternate timer counter registers (ACRH, ACRL) to a value
of $FFFC.
Clears all the interrupt enables and the output level bit (OLVL) in the
timer control register (TCR).
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
April 30, 1998
RESETS
GENERAL RELEASE SPECIFICATION
5-5

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