mpc8360e Freescale Semiconductor, Inc, mpc8360e Datasheet - Page 105

• Manufacturer Part Number: mpc8360e
• Description: Mpc8360e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

24.1
The device includes two PLLs.
24.2
Each of the PLLs listed above is provided with power through independent power supply pins (AV
AV
will be derived directly from V
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of package, without the inductance of vias.
Figure 55
24.3
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the device system, and the device itself
requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer
place at least one decoupling capacitor at each V
decoupling capacitors should receive their power from separate V
Freescale Semiconductor
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
DD
1. The platform PLL (AV
2. The e300 core PLL (AV
2 respectively). The AV
input. The frequency ratio between the platform and CLKIN is selected using the platform PLL
ratio configuration bits as described in
frequency ratio between the e300 core clock and the platform clock is selected using the e300
PLL ratio configuration bits as described in
System Clocking
PLL Power Supply Filtering
Decoupling Recommendations
shows the PLL power supply filter circuit.
V
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Figure 55. PLL Power Supply Filter Circuit
10 Ω
level should always be equivalent to V
1) generates the platform clock from the externally supplied CLKIN
2) generates the core clock as a slave to the platform clock. The
through a low frequency filter scheme such as the following.
2.2 µF
Section 22.1, “System PLL
DD
GND
Section 22.2, “Core PLL
, OV
Low ESL Surface Mount Capacitors
Figure
DD
2.2 µF
, GV
55, one to each of the five AV
DD
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, and LV
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AV
, OV
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pin being supplied to minimize
n
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, and preferably these voltages
Configuration.”
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, GV
Configuration.”
pins of the device. These
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System Design Information
, LV
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, and GND
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pins. By
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1,
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