mpc8360e Freescale Semiconductor, Inc, mpc8360e Datasheet - Page 88

• Manufacturer Part Number: mpc8360e
• Description: Mpc8360e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

Clocking
Figure 54
CFG_CLKIN_DIV
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. Note that in PCI host mode, the primary
clock input also depends on whether PCI clock outputs are selected with RCWH[PCICKEN]. When the
device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is selected
(RCWH[PCICKEN] = 1), CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and
the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input
selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn]
parameters select whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.The
OCCR[PCIOENn] parameters enable the PCI_CLK_OUTn respectively.
88
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
CLKIN
shows the internal distribution of clocks within the MPC8358E.
ce_clk to QUICC Engine block
Engine
QUICC
MPC8358E
PLL
System
PLL
Figure 54. MPC8358E Clock Subsystem
e300 core
PCI Clock
Clock
Divider
Unit
csb_clk
csb_clk to rest
of the device
ddr1_clk
lb_clk
Core PLL
LBIU
/n
DDRC
DLL
core_clk
/2
MEMC1_MCK[0:5]
MEMC1_MCK[0:5]
LCLK[0:2]
LSYNC_OUT
LSYNC_IN
PCI_CLK_OUT[0:2]
PCI_CLK/
PCI_SYNC_IN
PCI_SYNC_OUT
Freescale Semiconductor
Local Bus
Memory
Device
DDRC
Memory
Device