mpc8360e Freescale Semiconductor, Inc, mpc8360e Datasheet - Page 91

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mpc8360e

Manufacturer Part Number
mpc8360e
Description
Mpc8360e Powerquicc Ii Pro Family
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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22.1
The system PLL is controlled by the RCWL[SPMF] and RCWL[SVCOD] parameters.
multiplication factor encodings for the system PLL.
The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in
The system VCO frequency is derived from the following equations:
Freescale Semiconductor
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
System PLL Configuration
The VCO divider must be set properly so that the system VCO frequency is
in the range of 600-1400 MHz.
RCWL[SVCOD]
Table 70. System PLL Multiplication Factors
RCWL[SPMF]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 71. System PLL VCO Divider
00
01
10
11
NOTE
System PLL Multiplication
VCO Divider
Reserved
Reserved
Factor
× 16
× 10
× 11
× 12
× 13
× 14
× 15
× 2
× 3
× 4
× 5
× 6
× 7
× 8
× 9
4
8
2
Table
Table 70
71.
shows the
Clocking
91

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