mpc8360e Freescale Semiconductor, Inc, mpc8360e Datasheet - Page 37

• Manufacturer Part Number: mpc8360e
• Description: Mpc8360e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

Figure 19
Freescale Semiconductor
At recommended operating conditions with LV
GTX_CLK125 reference clock duty cycle
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
3. For 10 and 100 Mbps, t
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
5. Duty cycle reference is LV
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
7. In rev 2.0 silicon, due to errata, t
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
RGMII and RTBI timing. For example, the subscript of t
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
will be added to the associated clock signal.
as the minimum duty cycle is not violated and stretching occurs for no more than three t
between.
option 1, and 1.8 for UCC2 option 2. In rev2.1 silicon, due to errata, t
-0.9 for UCC2 option 2, and t
Please refer to QE_ENET10 in the device errata document. UCC1 does meet t
(At Transmitter)
shows the RGMII and RTBI AC timing and multiplexing diagrams.
RXD[8:5][3:0]
RXD[7:4][3:0]
TXD[8:5][3:0]
TXD[7:4][3:0]
GTX_CLK
(At PHY)
RX_CLK
(At PHY)
RX_CTL
TX_CLK
TX_CTL
Figure 19. RGMII and RTBI AC Timing and Multiplexing Diagrams
Table 35. RGMII and RTBI AC Timing Specifications (continued)
RGT
DD
scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
/2.
SKRGTKHDV
SKRGTKHDX
DD
RXD[3:0]
TXD[3:0]
RXD[4]
TXD[4]
TXEN
RXDV
maximum is 0.75 ns for UCC1 and UCC2 option 1 and 0.85 for UCC2 option 2.
of 2.5 V ± 5%.
minimum is -2.3 ns and t
RXD[8:5]
RXD[7:4]
TXD[8:5]
TXD[7:4]
RXERR
TXERR
RXD[9]
TXD[9]
t
G125H
RGT
/t
represents the TBI (T) receive (RX) clock. Note also that the
G125
UCC Ethernet Controller: Three-Speed Ethernet, MII Management
t
t
SKRGTKHDX
SKRGTKHDX
SKRGTKHDV
SKRGTKHDX
47
t
RGTH
SKRGTKHDX
maximum is 1 ns for UCC1, 1.2 ns for UCC2
minimum is -0.65 ns for UCC2 option 1 and
—
RGT
t
RGT
minimum for rev2.1 silicon.
of the lowest speed transitioned
53
t
t
SKRGTKHDX
SKRGTKHDX
%
37