mpc8360e Freescale Semiconductor, Inc, mpc8360e Datasheet - Page 52

• Manufacturer Part Number: mpc8360e
• Description: Mpc8360e Powerquicc Ii Pro Family
• Manufacturer: Freescale Semiconductor, Inc

I
Figure 33
Figure 34
52
All values refer to V
2
C
MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device
(including hysteresis)
Noise margin at the HIGH level for each connected device
(including hysteresis)
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the V
3. The maximum t
4. C
SDA
SCL
(reference)(state)
symbolizes I
clock reference (K) going to the high (H) state or setup time. Also, t
the data with respect to the start condition (S) went invalid (X) relative to the t
(L) state or hold time. Also, t
condition (P) reaching the valid state (V) relative to the t
time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
bridge the undefined region of the falling edge of SCL.
B
= capacitance of one bus line in pF.
provides the AC test load for the I
shows the AC timing diagram for the I
S
IH
(min) and V
2
t
C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
I2CF
for inputs and t
t
I2CL
t
I2SXKL
I2DVKH
Output
Parameter
IL
has only to be met if the device does not stretch the LOW period (t
Table 45. I
(max) levels (see
I2PVKH
(first two letters of functional block)(reference)(state)(signal)(state)
Figure 34. I
t
symbolizes I
I2DXKL
2
C AC Electrical Specifications (continued)
Figure 33. I
Table
Z
t
I2DVKH
0
= 50 Ω
44).
t
2
I2CH
2
C.
C Bus AC Timing Diagram
2
C timing (I2) for the time that the data with respect to the stop
2
t
I2SXKL
2
C bus.
C AC Test Load
I2C
clock reference (K) going to the high (H) state or setup
Symbol
t
t
I2PVKH
Sr
I2KHDX
t
V
V
I2CF
NH
NL
I2SXKL
t
I2SVKH
1
t
I2KHKL
R
L
(first two letters of functional block)(signal)(state)
symbolizes I
= 50 Ω
20 + 0.1 C
0.1 × OV
0.2 × OV
I2C
Min
0.6
1.3
clock reference (K) going to the low
for outputs. For example, t
t
DD
DD
I2PVKH
b
OV
2
4
C timing (I2) for the time that
IHmin
DD
t
I2CR
I2CL
/2
of the SCL signal) to
Max
) of the SCL signal.
Freescale Semiconductor
300
—
—
—
—
P
t
I2CF
Unit
I2DVKH
S
ns
μs
μs
V
V
I2C