isp1504a NXP Semiconductors, isp1504a Datasheet - Page 56

• Manufacturer Part Number: isp1504a
• Description: Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 42.
Table 43.
ISP1504A_ISP1504C_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 4
3
2
1 to 0
Symbol
-
BVALID_FALL
BVALID_RISE
-
Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation
Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description
10.1.13 Vendor-specific registers
10.1.14 Power Control register
R/W/S/C
10.2 Extended register set
7
0
Addresses 30h to 3Fh contain vendor-specific registers.
This register controls various aspects of the ISP1504.
the register.
Addresses 00h to 3Fh of the extended register set directly map to the immediate set. This
means a read, write, set or clear operation to these extended addresses will operate on
the immediate register set.
Addresses 40h to FFh are not implemented. Operating on these addresses may result in
undefined behavior of the PHY.
Description
reserved; the link must never write logic 1 to these bits
BVALID Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID
changes from HIGH to LOW, the ISP1504 will send an RXCMD to the link with the ALT_INT bit
set to logic 1.
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging
purposes. The session valid comparator should be used instead.
BVALID Rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID
changes from LOW to HIGH, the ISP1504 will send an RXCMD to the link with the ALT_INT bit
set to logic 1.
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging
purposes. The session valid comparator should be used instead.
reserved; the link must never write logic 1 to this bit
R/W/S/C
6
0
reserved
R/W/S/C
5
0
Rev. 03 — 7 April 2008
R/W/S/C
4
0
BVALID_
R/W/S/C
FALL
3
0
ISP1504A; ISP1504C
Table 42
BVALID_
R/W/S/C
RISE
ULPI HS USB OTG transceiver
2
0
shows the bit allocation of
R/W/S/C
1
0
© NXP B.V. 2008. All rights reserved.
reserved
R/W/S/C
0
0
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