adm6996f Infineon Technologies Corporation, adm6996f Datasheet
adm6996f
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... An Infineon Technologies Company ADM6996F 6 port 10/100 Mb/s Single Chip Ethernet Switch Controller Infineon-ADMtek Co Ltd Information in this document is provided in connection with Infineon-ADMtek Co Ltd products. Infineon- ADMtek Co Ltd may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” ...
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... October 2003 17 November 2003 12 January 2004 28 April 2004 Customer Support Infineon-ADMtek Co Ltd, 2F, No.2, Li-Hsin Rd., Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Sales Information Tel + 886-3-5788879 Fax + 886-3-5788871 Version Change 1.0 1. First release of ADM6996F 1.01 2. Updated Section 4.3.12 & 3.4 1.02 3. Updated Section 5.3 5.3.8 & 5.3.9 1.03 Infineon ADMtek updated logo V1.03 ...
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... NRZI/NRZ and Serial/Parallel Decoder.................................................. 3-2 3.4.4 Data De-scrambling................................................................................. 3-3 3.4.5 Symbol Alignment .................................................................................... 3-3 3.4.6 Symbol Decoding ..................................................................................... 3-3 3.4.7 Valid Data Signal..................................................................................... 3-3 3.4.8 Receive Errors ......................................................................................... 3-4 3.4.9 100Base-X Link Monitor.......................................................................... 3-4 3.4.10 Carrier Sense ........................................................................................... 3-4 3.4.11 Bad SSD Detection................................................................................... 3-4 3.4.12 Far-End Fault .......................................................................................... 3-5 3.5 100Base-TX Transceiver ................................................................................. 3-5 3.5.1 Transmit Drivers...................................................................................... 3-5 3.5.2 Twisted-Pair Receiver.............................................................................. 3-5 3.6 10Base-T Module............................................................................................. 3-5 3.6.1 Operation Modes ..................................................................................... 3-6 3.6.2 Manchester Encoder/Decoder ................................................................. 3-6 3.6.3 Transmit Driver and Receiver ................................................................. 3-6 3.6.4 Smart Squelch .......................................................................................... 3-6 ADM6996F V1.03 i ...
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... VLAN mapping table registers, offset: 0x22h ~ 0x13h ............................ 4-4 4.3.15 Reserved Register, offset: 0x27h ~ 0x23h................................................ 4-4 4.3.16 Port0, 1 PVID bit Configuration Register, offset: 0x28h ............. 4-1 4.3.17 Port2, 3 PVID bit Configuration Register, offset: 0x29h ............. 4-1 4.3.18 Port4, 5 PVID bit 11~4 Configuration Register, offset: 0x2ah ............... 4-1 4.3.19 Port6, 7 PVID bit 11~4 Configuration Register, offset: 0x2bh ............... 4-1 ADM6996F V1.03 ii ...
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... DC Characteristics ........................................................................................... 5-2 5.2.1 Absolute Maximum Rating....................................................................... 5-2 5.2.2 Recommended Operating Conditions ...................................................... 5-2 5.2.3 DC Electrical Characteristics for 3.3V Operation .................................. 5-2 5.3 AC Characteristics ........................................................................................... 5-3 5.3.1 Power On Reset........................................................................................ 5-3 5.3.2 EEPROM Interface Timing...................................................................... 5-3 5.3.3 10Base-TX MII Input Timing ................................................................... 5-4 5.3.4 10Base-TX MII Output Timing ................................................................ 5-4 5.3.5 100Base-TX MII Input Timing ................................................................. 5-5 5.3.6 100Base-TX MII Output Timing .............................................................. 5-5 5.3.7 SMI Timing............................................................................................... 5-6 5.3.8 GPSI(7-wire) Input Timing ...................................................................... 5-6 ADM6996F V1.03 iii ...
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... GPSI(7-wire) Output Timing ................................................................... 5-7 5.3.10 Serial Management Interface (MDC/MDIO) Timing .............................. 5-8 Chapter 6 Packaging...................................................................................................... 6-1 6.1 128 Pin PQFP Outside Dimension................................................................... 6-1 Figure 1-1 ADM6996F Block Diagram........................................................................... 1-3 Figure 2-1 4 TP/FX PORT + 2 MII PORT 128 Pin Diagram.......................................... 2-1 ADM6996F List of Figures V1.03 iv ...
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... Control Pause packet in Full-Duplex mode to prevent packet loss when buffers are full. When Back Pressure is enabled, and there is no receive buffer available for the incoming packet, the ADM6996F will issue a JAM pattern on the receiving port in Half Duplex mode and transmit the 802.3x Pause packet back to receiving end in Full Duplex mode. ...
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... Supports PHY status output for management system. x 25M Crystal only for the whole system. x 128 QFP package with 0.18um technology. 1.8V/3.3V power supply. x 1.3 Applications ADM6996F in 128-pin PQFP: Infineon-ADMtek Co Ltd SOHO 5-port switch 5-port switch + Router with MII CPU interface. Product Review 1-2 ...
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... PORT2 ... PORTN A/D DIGITAL CONVERTER EQUALIZER DRIVER MLT3 Converter BIAS CLOCK GENERATOR Figure 1-1 ADM6996F Block Diagram Bit Error Rate Canonical Format Indicator Collision Cyclic Redundancy Check Carrier Sense Chip Select Destination Address Data Input Data Output EEPROM Data Input EEPROM Data Output ...
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... ADM6996F EESK ESD FEFI FET FLP GND GPSI IPG LFSR MAC MDIX MII NRZI NRZ PCS PHY PLL PMA PMD QoS QFP RST RXCLK RXD RXDV RXER RXN RXP SA SOHO SSD SQE TOS TP TTL TXCLK TXD TXEN TXN TXP Infineon-ADMtek Co Ltd ...
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... ADM6996F 1.6 Conventions 1.6.1 Data Lengths qword dword word byte nibble 1.6.2 Pin Types Pin Type I O I/O OD SCHE PD PU 1.6.2 Register Types Register Type Infineon-ADMtek Co Ltd 64-bits 32-bits 16-bits 8 bits 4 bits Description Input Output Bi-directional Open drain Schmitt Trigger internal pull-down internal pull-up Description ...
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... GNDIK 119 RC 120 XI 121 XO 122 VCCPLL 123 GNDPLL 124 CONTROL 125 VREF 126 GNDBIAS 127 RTX 128 VCCBIAS Infineon-ADMtek Co Ltd ADM6996F Figure 2-1 4 TP/FX PORT + 2 MII PORT 128 Pin Diagram Interface Description 64 GNDIK 63 (GFCEN) P5TXD0 62 P4FX 61 (P5GPSI) P5TXD1 60 P5TXD2 59 P5TXD3 58 P5COL 57 P5CRS 56 P5RXD3 55 ...
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... ADM6996F 2.2 Pin Description by Function ADM6996F pins are categorized into one of the following groups: ƒSection 2.2.1 Twisted Pair Interface ƒSection 2.2.2 5th Port (MII) Interfaces ƒSection 2.2.3 6th Port (MII) Interfaces ƒSection 2.2.4 LED Interface ƒSection 2.2.5 EEPROM/Management Interface ƒSection 2.2.6 Power/Ground, 48 pins ƒ ...
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... ADM6996F Pin Name P4FX P4TXEN P4RXD[0] P4RXD[3:1] 102, 101, P4RXDV P4RXER P4COL P4CRS P4RXCLK P4TXCLK DHALFP4 LNKFP4 SPDTNP4 2.2.3 6th Port (MII) Interfaces Pin Name P5TXD[0] Setting GFCEN Infineon-ADMtek Co Ltd Pin# Type Descriptions 62 I Port4 FX/TX mode select. Internal pull down Port4 as FX port. ...
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... ADM6996F Pin Name P5TXD[1] Setting P5GPSI P5TXD[3:2] 59, 60 P5TXEN Setting PHYAS0 P5RXD[3:0] 56, 55, 54, 53 P5RXDV P5RXER P5COL P5CRS P5RXCLK P5TXCLK DHALFP5 Infineon-ADMtek Co Ltd Pin# Type Descriptions “1” to enable flow-control (default ), “0” to disable flow- control. 61 I/O, MII Transmit Data bit 1 8mA Synchronous to the rising edge of TXCLK ...
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... ADM6996F Pin Name LNKFP5 SPDTNP5 2.2.4 LED Interface Pin Name LNKACT[3:0] 96, 97, DUPCOL[3] DUPCOL[2] Setting BPEN DUPCOL[1] Setting PHYAS1 DUPCOL[0] Setting ANEN LDSPD[3:0] 48, 47, 43, 42 Infineon-ADMtek Co Ltd Pin# Type Descriptions Internal pull down Port5 MII Port Hardware Link input pin. PD Low: Link OK. High: Link Off. ...
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... ADM6996F 2.2.5 EEPROM/Management Interface Pin Name EDO EECS EECK Setting XOVEN EDI Setting LEDMODE 2.2.6 Power/Ground, 48 pins Pin Name GNDA 4,5,12, 13, 20, 27, 28, 34, 35 VCCA2 1, 9, 17, 24, 38 VCCAD 8, 16, 23, 31 GNDBIAS VCCBIAS GNDPLL VCCPLL GNDIK 45, 64, 76, 83, 93, VCCIK 46, 65, 75, 82, 94, GNDO 50, 69, 70, 87, 99, ...
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... ADM6996F Pin Name Control RTX VREF CFG0 MDIO MDC TEST Infineon-ADMtek Co Ltd Pin# Type Descriptions 8mA 124 O FET Control Signal. The pin is used to control FET for 3.3V to 1.8V regulator. 127 Analog TX Resistor. Add 1.1K %1 resister to GND. 125 Analog Analog Reference Voltage. 119 I, RC Input for Power On reset. Reset input pin. ...
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... Module The ADM6996F implements 100Base-X compliant PCS and PMA and 100Base-TX compliant TP-PMD as illustrated in Figure 2. Bypass options for each of the major functional blocks within the 100Base-X PCS provides flexibility for various applications. 100Mbits/s PHY loop back is included for diagnostic purpose. ...
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... Decision Feedback techniques meet the requirement of BER less than 10-12 for transmission on CAT5 twisted pair cable ranging from 0 to 120 meters. 3.4.3 NRZI/NRZ and Serial/Parallel Decoder The recovered data is converted from NRZI to NRZ. The data is not necessarily aligned to 4B/5B code group’s boundary. Infineon-ADMtek Co Ltd. The ADM6996F implements the 100Base-X Function Description 3-2 ...
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... Symbol Alignment The symbol alignment circuit in the ADM6996F determines code word alignment by recognizing the /J/K delimiter pair. This circuit operates on unaligned data from the de- scrambler. Once the /J/K symbol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary ...
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... If this condition is detected, then the ADM6996F will assert RXER and present RXD[3:0] = 1110 to the internal MII for the cycles hat correspond to received 5B code- groups until at least two idle code-groups are detected. Once at least two idle code groups are detected, RXER and CRS become de-asserted ...
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... The ADM6996F uses an adaptive equalizer that changes filter frequency response in accordance with cable length. The cable length is estimated based on the incoming signal strength. The equalizer tunes itself automatically for any cable length to compensate for the amplitude and phase distortions incurred from the cable ...
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... Jabber and SQE test functions x Polarity detection and correction 3.6.1 Operation Modes The ADM6996F 10Base-T module is capable of operating in either half-duplex mode or full-duplex mode. In half-duplex mode, the ADM6996F functions as an IEEE 802.3 compliant transceiver with fully integrated filtering. The COL signal is asserted during collisions or jabber events, and the CRS signal is asserted during transmit and receive ...
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... CRS is asserted only due to receive activity. 3.8 Jabber Function The jabber function monitors the ADM6996F output and disables the transmitter if it attempts to transmit a longer than legal sized packet. If TXEN is high for greater than 24ms, the 10Base-T transmitter will be disabled. Once disabled by the jabber function, the transmitter stays disabled for the entire time that the TXEN signal is asserted ...
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... Memory Block ADM6996F build in memory is divided as two blocks. One is MAC addressing table and another one is data buffer. MAC address Learning Table size is 2048 entry with each entry occupy eight bytes length. These eight bytes data include 6 bytes source address, VLAN information, Port information and Aging counter ...
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... MAC addresses. Address is stored in the Address Table. The ADM6996F searches for the Source Address (SA incoming packet in the Address Table and acts as below: If the SA was not found in the Address Table (a new address), the ADM6996F waits until the end of the packet (non-error packet) and updates the Address Table. If the SA was found in the Address Table, then aging value of each corresponding entry will be reset to 0 ...
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... If the UNICAST address and the address was not found, the ADM6996F treats multicast packet and forwards across the bridge the Multicast address, the packet is forwarded across the bridge. ...
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... CRC. Dribbling packing with good CRC value will accept by ADM6996F. In case of bypass mode enabled, ADM6996F will support tag and untagged packets with size up to 1522 bytes. In case of non-bypass mode, ADM6996F will support tag packets up to 1526bytes, untagged packets up to 1522bytes ...
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... ADM6996F also supports 16 802.1Q VLAN groups. In VLAN four bytes tag include twelve VLAN ID. ADM6996F learn user define four bits of VID. If user need to use this function, two EEPROM registers are needed to be programmed first : * Port VID number at EEPROM register 0x01h~0x09h bit 13~10, register 0x28h~0x2bh and register 0x2ch bit 7~0: ADM6996F will check coming packet ...
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... VLAN and TOS VLAN first: ADM6996F check VLAN three priority bit first then IP TOS priority bits TOS first: ADM6996F check IP TOS three priority bit first then VLAN three priority bits. If port set at VLAN/TOS priority but receiving packet without VLAN or TOS information then port base priority will be used ...
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... ADM6996F ADM6996F LED is active Low signal. Dupcol0 & Dupcol1 will check external signal at Reset time. If external signal add pull high then LED will active Low. If external signal add pull down resister then LED will drive high. Link /Ac t Infineon-ADMtek Co Ltd. Single ...
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... ADM6996F Chapter 4 Register Description 4.1 EEPROM Content EEPROM provides ADM6996F many options setting such as: x Port Configuration: Speed, Duplex, Flow Control Capability and Tag/ Untag. x VLAN & TOS Priority Mapping x Broadcast Storming rate and Trunk. x Fiber Select, Auto MDIX select x VLAN Mapping x Per Port Buffer number 4 ...
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... RO The value must be 4154h(AT) Note: ADM6996F will check register 0 value before read all EEPROM content. If this value not match with 0x4154h then other values in EEPROM will be useless. ADM6996F will use internal default value. User cannot write Signature register when programming ADM6996F internal register. ...
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... R/W Enable port-base priority. 1: Port Base Priority. 0: VLAN or TOS. If packet without VLAN or TOS then port priority turn on. Note: If this bit turn on then ADM6996F will not check TOS or VLAN as priority reference. ADM6996F will check port base priority only. ADM6996F default is bypass mode which checks port base priority only. ...
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... R/W Enable Trunk. 1: enable Port3 Trunk port. 0: disable. 6 R/W Enable IPG leveling. 1/92 bit. 0/96 bit. Note: When this bit is enable ADM6996F will transmit packet out at 92 bit IPG to clean buffer. If user disables this function then ADM6996F will transmit packet at 96 bit. 5:0 RO Reserved 4.3.5 Reserved Register, offset: 0x0ch~0x0dh ...
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... Ethernet Packet from Layer 2 Preamble/SFD Destination (6 bytes) Byte 0~5 4.3.9 VLAN Packet ADM6996F will check packet byte 12 &13. If byte[12:13]=8100h then this packet is a VLAN packet Tag Protocol TD 8100 Byte 12~13 Byte 14~15: Tag Control Information TCI Bit[15:13]: User Priority 7~0 Bit 12: Canonical Format Indicator (CFI) Bit[11~0]: VLAN ID ...
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... ADM6996F 4.3.10 TOS IP Packet ADM6996F check byte 12 &13 if this value is 0800h then ADM6996F knows this is a TOP priority packet. Type 0800 Byte 12~13 IP header define Byte 14 Bit[7:0]: IP protocol version number & header length. Byte 15: Service type Bit[7~5]: IP Priority (Precedence ) from 7~0 Bit 4: No Delay (D) ...
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... R/W MAC Clone enable 0: Normal mode. Learning with SA only. ADM6996F fill/search MAC table only. 1: MAC Clone mode. Learning with SA, VID0. ADM6996F fill/search MAC table with VID0. This bit can let chip learn two same addresses with different VID0. ...
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... Port1 4 100/10 LAN Port VLAN & WAN Function In this application, the CPU’s MDC/MDIO interface is used to access all PHY and switch registers in ADM6996F. Port 4 is used as the WAN port and Port 5 is used to connect the Infineon-ADMtek Co Ltd ISA 10M Half NIC ...
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... ADM6996F CPU. Because the WAN port need to be isolated from the LAN ports due to frames are different and need to be translated by CPU. CPU will act as the bridge to transmit, receive and translate frames between WAN and LAN. This isolated PHY can help to reduce the BOM costs and improve the Gateway router’ ...
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... ADM6996F 4.3.16 Port0, 1 PVID bit Configuration Register, offset: 0x28h Bits Type Description 15:8 RO Reserved 7:0 R/W Port0 PVID bit 11~4. These 8 bits combine with register 0x01h Bit [13~10] as full 12 bit VID. 4.3.17 Port2, 3 PVID bit Configuration Register, offset: 0x29h Bits Type Description 15:8 RO Reserved 7:0 R/W Port1 PVID bit 11~4. These 8 bits combine with register 0x03h Bit[13~10] as full 12 bit VID ...
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... R/W Port5 PVID bit 11~4. These 8 bits combine with register 0x09h Bit[13~10] as full 12 bit VID. Note: Bit[10:8]: VLAN Tag shift register. ADM6996F will select 4 bit from total 12 bit VID as VLAN group reference. Bit[15:12]: IEEE 802.3 reserved DA forward or drop police. 4.3.21 Reserved Register, offset: 0x2dh ...
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... ADM6996F Bits Type Description 5 R/W MAC Clone Enable Bit[1]. 4:3 R/W Reserved 2 R/W Reserved 1 R/W Reserved 0 R/W Reserved 4.3.25 Bandwidth Control Register0~3, offset: 0x31h Bits Type Description 15 R/W Receive Packet Length Counted on the Source Port The switch will add length to the P3 counter. 14:12 R/W Port 3 Meter Threshold Control. Reference table below. ...
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... EEPROM WRITE instruction only. If there is any Protection instruction before or after the EEPROM WRITE instruction, CPU needs to generate separated CS signal cycle for each Protection & WRITE instruction. CPU can directly program ADM6996F after 30ms of Reset signal rising edge with or without EEPROM Infineon-ADMtek Co Ltd ...
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... It’s a little different with the timing on the writing EEPROM. See below graph. One must be carefull when CS goes down after write a command, SK must issue at least one clock. This is a difference between the ADM6996F with EEPROM write timing. If the system is without EEPROM then user must write ADM6996F internal register by 93C66 timing. If user uses EEPROM then the writing timing is dependent on EEPROM type ...
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... ADM6996F 4.5 Serial Register Map Register 0x00h 0x01h 0x02h 0x03h 0x04h 0x05h 0x06h 0x07h 0x08h 0x09h 0x0ah 0x0bh 0x0ch 0x0dh 0x0eh 0x0fh 0x10h 0x11h 0x12h 0x13h 0x14h 0x15h 0x16h 0x17h 0x18h 0x19h 0x1ah 0x1bh 0x1ch 0x1dh 0x1eh 0x1fh 0x20h 0x21h 0x22h 0x23h ...
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... ADM6996F Register 0x2ah 0x2bh 0x2ch 0x2dh 0x2eh 0x2fh 0x30h 0x31h 0x32h 0x33h 0x34h 0x35h 0x36h 0x37h 0x38h 0x39h 0x3ah 0x3bh 0x3ch 4.6 Serial Register Description 4.6.1 Chip Identifier Register, offset: 0x00h Bits Type Description 31:4 RO 0x0007101h 3:0 RO 0000 (Version number) 4.6.2 Port Status 0 Register, offset: 0x01h ...
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... ADM6996F Bits Type Description 1: 802.3X on for full duplex or back pressure on for half duplex. 0: Flow Control Disable 26 RO Port 3 Duplex Status 1: Full Duplex. 0: Half Duplex Port 3 Speed Status: 1: 100Mb Mb Port 3 Linkup Status: 1: Link is established. 0: Link is not established Reserved ...
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... ADM6996F Bits Type Description 5 RO Reserved 4 RO Reserved 3 RO Port 0 Flow Control Enable 1: 802.3X on for full duplex or back pressure on for half duplex. 0: Flow Control Disable 2 RO Port 0 Duplex Status 1: Full Duplex. 0: Half Duplex Port 0 Speed Status: 1: 100Mb Mb Port 0 Linkup Status: 1: Link is established ...
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... ADM6996F Bits Type Description 19:18 RO Port 3 Cable Broken Length 17 RO Reserved 16:15 RO Reserved 14 RO Port 2 Cable Broken 13:12 RO Port 2 Cable Broken Length 11 RO Reserved 10:9 RO Reserved 8 RO Port 1 Cable Broken 7:6 RO Port 1 Cable Broken Length 5 RO Reserved 4:3 RO Reserved 2 RO Port 0 Cable Broken 1:0 RO Port 0 Cable Broken Length 4 ...
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... ADM6996F Bits Type Description 15 RO Overflow of Port 3 Transmit Packet Byte Count 14 RO Reserved 13 RO Overflow of Port 2 Transmit Packet Byte Count 12 RO Reserved 11 RO Overflow of Port 1 Transmit Packet Byte Count 10 RO Reserved 9 RO Overflow of Port 0 Transmit Packet Byte Count 8 RO Overflow of Port 5 Transmit Packet Count ...
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... Register +1, Register ( Register is even number). Register, Register-1(Register is Odd number). Example: Read Register 00h then ADM6996F will drive 0x01h & 0x00h. Read Register 03h then ADM6996F will drive 0x03h & 0x02h. Idle: EESK must send at least one clock at idle time. ...
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... ADM6996F Preamble: At least 32 continuous “1”. Start: 01(2 bits) Opcode bits, Reset command) Device Address: Chip physical address as PHYAS[1:0]. Reset_type: Reset counter by port number or by counter index. 1: Clear dedicate port’s all counters. 0: Clear dedicate counter. Port_number or counter index: User define clear port or counter. ...
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... ADM6996F Bits Type Name 12 R/W ANEN 11 R/W PDN 10 R/W ISO 9 R/W, ANEN_RST Restart Auto Negotiation SC 8 R/W DPLX 7 R/W COLTST Infineon-ADMtek Co Ltd Description Link speed is selected by this bit or by auto negotiation if bit 12 of this register is set (in which case, the value of this bit is ignored fiber mode, 0.13 is always 1. Any write to this bit will have no effect ...
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... ADM6996F Bits Type Name 6 RO SPEED_MSB Speed Selection MSB 5:0 RO Reserved 4.8.2 Status Register, offset: 0x01 Bits Type Name 15 RO CAP_T4 14 RO CAP_TXF 13 RO CAP_TXH 12 RO CAP_TF 11 RO CAP_TH 10 RO CAP_T2 9:7 RO Reserved 6 RO CAP_SUPR 5 RO AN_COMP Infineon-ADMtek Co Ltd Description to be asserted in response to the assertion of TXEN. ...
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... ADM6996F Bits Type Name 4 RO REM_FLT 3 RO CAP_ANEG Auto Negotiation Ability 2 RO LINK 1 RO JAB 0 RO EXTREG 4.8.3 PHY Identifier Register, offset: 0x02 Bits Type Name 15:0 RO PHY- ID[15:0] 4.8.4 PHY Identifier Register, offset: 0x03 Bits Type Name 15:10 RO PHY- ID[15:0] 9:4 RO PHY- Infineon-ADMtek Co Ltd Description Remote Fault Detect 1 – ...
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... ADM6996F Bits Type Name ID[15:0] 3:0 RO PHY- ID[15:0] Note: Register 3 = 0xCC10 4.8.5 Auto Negotiation Advertisement Register, offset : 0x04 Bits Type Name R/W Reserved Reserved 11 R/W ASM_DIR 10 R/W PAUSE R/W TX_FDX 7 R/W TX_HDX 6 R/W 10_FDX 5 R/W 10_HDX Infineon-ADMtek Co Ltd Description IEEE Revision No. Description Next Page This bit is defaults to 1, indicating that D7001 is next page capable ...
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... ADM6996F Bits Type Name 4:0 RO Selector Field These 5 bits are hardwired to 00001b, indicating that the 4.8.6 Auto Negotiation Link Partner Ability Register, offset: 0x05 Bits Type Name 15 RO NPAGE 14 RO ACK Reserved 11 RO LP_DIR 10 RO LP_PAU 9 RO LP_T4 8 RO LP_FDX 7 RO LP_HDX ...
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... ADM6996F Bits Type Name 3 RO LPNPABLE Link Partner Next Page Able 2 RO NPABLE 1 RO PGRCV 0 RO LPANABLE Link Partner Auto Negotiation Able 4.8.8 Next Page Transmit Register, offset: 0x07 Bits Type Name 15 RO TNPAGE 14 RO Reserved 13 R/W TMSG 12 R/W TACK2 11 RO TTOG 10:0 R/W TFLD[10:0] 4.8.9 Link Partner Next Page Register, offset: 0x08 ...
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... TX/FX Interface 5.1.1 TP Interface TXP TXN ADM6995 RXP RXN Transformer requirement: . TX/RX rate 1:1 . TX/RX central tap connect together to VCCA2. User can change TX/RX pin for easy layout but do not change polarity. ADM6996F supports auto polarity on receiving side. 5.1.2 FX Interface TXP TXN ADM6995 RXP RXN Infineon-ADMtek Co Ltd 1:1 0.01U R1 49 ...
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... ADM6996F 5.2 DC Characteristics 5.2.1 Absolute Maximum Rating Symbol Parameter V Power Supply CC Vcca2 TX line driver Vccpll PLL voltage Vccik Digital core voltage V Input Voltage IN Vout Output Voltage TSTG Storage Temperature PD Power Dissipation ESD ESD Rating 5.2.2 Recommended Operating Conditions Symbol Parameter Vcc Power Supply Vcca2 ...
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... ADM6996F 5.3 AC Characteristics 5.3.1 Power On Reset RST* All Configuration Pins Symbol Parameter TRST RST Low Period TCONF Start of Idle Pulse Width 5.3.2 EEPROM Interface Timing 0us EECS EESK tEWDD EEDO EEDI Symbol Parameter TESK EESK Period TESKL EESK Low Period TESKH EESK High Period ...
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... ADM6996F 5.3.3 10Base-TX MII Input Timing 0ns MII_RXCLK MII_RXDV MII_RXD MII_CRS Symbol Parameter tCK MII_RXCLK Period tCKL MII_RXCLK Low Period tCKH MII_RXCLK High Period tRXS MII_CRS, MII_RXDV and MII_RXD to MII_RXCLK rising setup tRXH MII_CRS, MII_RXDV and MII_RXD to MII_RXCLK rising hold 5.3.4 10Base-TX MII Output Timing ...
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... ADM6996F 5.3.5 100Base-TX MII Input Timing 0ns MII_RXCLK MII_RXDV MII_RXD MII_CRS Symbol Parameter tCK MII_RXCLK Period tCKL MII_RXCLK Low Period tCKH MII_RXCLK High Period tRXS MII_CRS, MII_RXDV and MII_RXD to MII_RXCLK rising setup tRXH MII_CRS, MII_RXDV and MII_RXD to MII_RXCLK rising hold 5.3.6 100Base-TX MII Output Timing ...
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... ADM6996F Symbol Parameter tCKH MII_TXCLK High Period tTXOD MII_TXD, MII_TXEN to MII_TXCLK Rising Output Delay 5.3.7 SMI Timing 0ns SDC SDIO Symbol Parameter T SDC Period CK T SDC Low Period CKL T SDC High Period CKH T SDIO to SDC rising setup time on SDS read/write cycle T SDIO to SDC rising hold time on ...
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... ADM6996F Symbol Parameter TCKH GPSI_RXCLK High Period TTXS GPSI_RXD, GPSI_CRS/COL to GPSI_RXCLK Rising Setup Time TTXH GPSI_RXD, GPSI_CRS/COL to GPSI_RXCLK Rising Hold Time 5.3.9 GPSI(7-wire) Output Timing 0ns GPSI_TXCLK GPSI_TXD tOD GPSI_TXEN Symbol Parameter TCK GPSI_TXCLK Period TCKL GPSI_TXCLK Low Period TCKH GPSI_TXCLK High Period ...
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... ADM6996F 5.3.10 Serial Management Interface (MDC/MDIO) Timing 0ns MDC MDIO (output) MDIO (input) Symbol Parameter T MDC Period CK T MDC Low Period CKL T MDC High Period CKH tOD MDC to MDIO Delay Time MDIO Input to MDC Setup Time tMDS MDIO Input to MDC Hold Time ...
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... ADM6996F Chapter 6 Packaging 6.1 128 Pin PQFP Outside Dimension Infineon-ADMtek Co Ltd 17.2 +/- 0.2 mm 14.0 +/- 0.1 mm 12.5 mm 0.5 mm Appendix 6-1 ...