adm6996f Infineon Technologies Corporation, adm6996f Datasheet - Page 54

• Manufacturer Part Number: adm6996f
• Description: 6 Port 10/100 Mb/s Single Chip Ethernet Switch Controller
• Manufacturer: Infineon Technologies Corporation

ADM6996F
Infineon-ADMtek Co Ltd
15
14
13
4.8
4.8.1 Control Register, offset: 0x00
Bits
Preamble: At least 32 continuous “1”.
Start: 01(2 bits)
Opcode: 01 (2 bits, Reset command)
Device Address: Chip physical address as PHYAS[1:0].
Reset_type: Reset counter by port number or by counter index.
Port_number or counter index: User define clear port or counter.
Idle: EECK must send at least one clock at idle time.
PHY Register Description
R/W,
Type Name
R/W LPBK
R/W SPEED_LSB Speed Selection LSB
SC
RST
1: Clear dedicate port’s all counters.
0: Clear dedicate counter.
Description
RESET
1 – PHY Reset
0 – Normal operation
Setting this bit initiates the software reset function that resets
the selected port, except for the phase-locked loop circuit. It
will re-latch in all hardware configuration pin values The
software reset process takes 25us to complete. This bit,
which is self-clearing, returns a value of 1 until the reset
process is complete.
1 – Enable loopback mode
0 – Disable Loopback mode
This bit controls the PHY loopback operation that isolates
the network transmitter outputs (TXP and TXN) and routes
the MII transmit data to the MII receive data path. This
function should only be used when auto negotiation is
disabled (bit12 = 0). The specific PHY (10Base-T or
100Base-X) used for this operation is determined by bits 12
and 13 of this register
0.6, 0.13
0
0
1
1
Loop Back Enable
0
1
0
1
10 Mbits/s
100 Mbits/s
1000 Mbits/s
Reserved
Register Description
Initial value
0x0h
0x0h
0x1h
4-2