adm6996f Infineon Technologies Corporation, adm6996f Datasheet - Page 26

• Manufacturer Part Number: adm6996f
• Description: 6 Port 10/100 Mb/s Single Chip Ethernet Switch Controller
• Manufacturer: Infineon Technologies Corporation

ADM6996F
Infineon-ADMtek Co Ltd.
3.10 Automatic Link Polarity Detection
3.11 Clock Synthesizer
3.12 Auto Negotiation
3.13 Memory Block
ADM6996F’s 10Base-T transceiver module incorporates an “automatic link polarity
detection circuit”. The inverted polarity is determined when seven consecutive link pulses
of inverted polarity or three consecutive packets are received with inverted end-of-packet
pulses. If the input polarity is reversed, the error condition will be automatically corrected
and reported in bit 5 of register 10h.
The ADM6996F implements a clock synthesizer that generates all the reference clocks
needed from a single external frequency source. The clock source must be a TTL level
signal at 25 MHz +/- 50ppm
The Auto Negotiation function provides a mechanism for exchanging configuration
information between two ends of a link segment and automatically selecting the highest
performance mode of operation supported by both devices. Fast Link Pulse (FLP) Bursts
provide the signaling used to communicate auto negotiation abilities between two devices
at each end of a link segment. For further detail regarding auto negotiation, refer to
Clause 28 of the IEEE 802.3u specification. The ADM6996F supports four different
Ethernet protocols, so the inclusion of auto negotiation ensures that the highest
performance protocol will be selected based on the ability of the link partner.
x 100Base-TX full duplex (highest priority)
x 100Base-TX half duplex
x 10Base-T full duplex
x 10Base-T half duplex (lowest priority)
ADM6996F build in memory is divided as two blocks. One is MAC addressing table and
another one is data buffer.
MAC address Learning Table size is 2048 entry with each entry occupy eight bytes
length. These eight bytes data include 6 bytes source address, VLAN information, Port
information and Aging counter.
Data buffer is divided to 256 bytes/block. ADM6996F buffer management is per port
fixed block number and all port share one global buffer. This architecture can get better
memory utilization and network balance on different speed and duplex test condition.
Received packet will separate as several 256 bytes/block and chain together. If packet
size more than 256 bytes then ADM6996F will chain two or more block to store
receiving packet.
Highest priority relative to the following list:
Function Description
3-8