adm6996f Infineon Technologies Corporation, adm6996f Datasheet - Page 15

• Manufacturer Part Number: adm6996f
• Description: 6 Port 10/100 Mb/s Single Chip Ethernet Switch Controller
• Manufacturer: Infineon Technologies Corporation

ADM6996F
Infineon-ADMtek Co Ltd
Pin Name
P5TXD[1]
Setting
P5GPSI
P5TXD[3:2]
P5TXEN
Setting
PHYAS0
P5RXD[3:0]
P5RXDV
P5RXER
P5COL
P5CRS
P5RXCLK
P5TXCLK
DHALFP5
56, 55, 54, 53
59, 60
Pin#
61
66
52
68
58
57
72
67
91
Type
8mA
8mA
8mA
I/O,
I/O,
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
I/O
I
I
I
I
I
I
I
I
Descriptions
“1” to enable flow-control (default ), “0” to disable flow-
control.
MII Transmit Data bit 1
Synchronous to the rising edge of TXCLK. These pins act
as MII TXD[1].
Setting
P5GPSI: Port 5 GPSI Enable.
At power-on-reset, latched as P5 GPSI Enable.
“0” to disable port 5 GPSI (default ), “1” to enable port 5
GPSI.
Port5 MII Transmit Data bit 3~2
Synchronous to the rising edge of TXCLK. These pins act
as MII TXD[3:2].
Port5 MII Transmit Enable. Internal pull down.
Setting
PHYAS0: Chip physical address for multiple chip application
on read EEPROM data. Internal pull down.
Power on reset value PHYAS0 combines with PHYAS1
PHYAS1
0
If there is no EEPROM then user must use 93C66 timing to
write chip’s register.
If user put 93C46 with correct Signature then user writes
chip register by 93C46 timing.
If user put 93C66 then data put in Bank0. User can write
chip register by 93C66 timing.
User must assert one SK cycle when CS at idle stage when
write chip internal register.
Port5 MII port receive data 3~0
These pins act as MII RXD[3:0]. Synchronous to the rising
edge of P5RXCLK. Internal pull down.
Port5 MII receive data valid.
Internal pull down.
Port5 MII Port Receive Error.
Internal pull down.
Port5 MII Port Collision input
Internal pull down.
Port5 MII Port Carrier Sense
Internal pull down.
Port5 MII Port Receive Clock Input
Port5 MII Port Transmit clock Input
Port5 MII Port Hardware Duplex input pin.
Low: Full Duplex. High: Half Duplex.
0
PHYAS0
Master(93C46)
Interface Description
2-4