fdc37m707 Standard Microsystems Corp., fdc37m707 Datasheet - Page 24

• Manufacturer Part Number: fdc37m707
• Description: Fdc37m707 Enhanced Super I/o Controller With Wake-up Features
• Manufacturer: Standard Microsystems Corp.

MAIN STATUS REGISTER
Address 3F4 READ ONLY
The Main Status Register is a read-only register
and indicates the status of the disk controller.
The Main Status Register can be read at any
BIT 0 - 1 DRV x BUSY
These bits are set to 1s when a drive is in the
seek portion of a command, including implied
and overlapped seeks and recalibrates.
BIT 4 COMMAND BUSY
This bit is set to a 1 when a command is in
progress.
command byte has been accepted and goes
inactive at the end of the results phase. If there
is
commands), this bit is returned to a 0 after the
last command byte.
no
result
RQM
This bit will go active after the
7
phase
DIO
6
*The 2Mbps data rate is only available if V
(Seek,
Table 11 - Default Precompensation Delays
DATA RATE
NON
DMA
500 Kbps
300 Kbps
250 Kbps
2 Mbps*
1 Mbps
5
Recalibrate
BUSY
CMD
4
PRECOMPENSATION
24
Reserved Reserved
time.
controller is ready to receive data via the Data
Register. It should be read before each byte
transferring to or from the data register except in
DMA mode. No delay is required when reading
the MSR after a data transfer.
BIT 5 NON-DMA
This
command and will be set to a 1 during the
execution phase of a command.
polled data transfers and helps differentiate
between the data transfer phase and the reading
of result bytes.
BIT 6 DIO
Indicates the direction of a data transfer once a
RQM is set.
indicates a write is required.
BIT 7 RQM
Indicates that the host can transfer data if set to
a 1. No access is permitted if set to a 0.
3
DELAYS
41.67 ns
20.8 ns
125 ns
125 ns
125 ns
mode
The MSR indicates when the disk
2
CC
is
A 1 indicates a read and a 0
= 5V.
selected
BUSY
DRV1
1
in
BUSY
DRV0
the
0
This is for
SPECIFY