w83l517g Winbond Electronics Corp America, w83l517g Datasheet - Page 46

• Manufacturer Part Number: w83l517g
• Description: Winbond Lpc I/o For Notebook W83l517d/ W83l517d-f
• Manufacturer: Winbond Electronics Corp America

Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary
format) from the divisor latches of the baudrate generator during a read or write operation. When this
bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt Control
Register can be accessed.
Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is
affected by this bit; the transmitter is not affected.
Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,
(1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check.
(2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.
BDLAB
BDLAB
BDLAB
ADDRESS BASE
+ 0
= 0
+ 0
= 0
+ 1
= 0
+ 2
+ 2
+ 3
+ 4
REGISTER
(Read Only)
(Write Only)
(Read Only)
(Write Only)
Transmitter
UART FIFO
Handshake
Receiver
Interrupt
Interrupt
Register
Register
Register
Register
Register
Register
Register
Control
Control
Control
Control
Status
Buffer
Buffer
UART
RBR
UCR
HCR
TBR
UFR
ICR
ISR
RX Data
TX Data
(ERDRI)
Terminal
Interrupt
Interrupt
Pending
Enable
Enable
(DLS0)
Length
Ready
Ready
Select
(DTR)
FIFO
RBR
Data
Data
Data
Bit 0
Bit 0
"0" if
Bit 0
0
TABLE 7-1 UART Register Bit Map
(ETBREI)
RX Data
Interrupt
Interrupt
Request
TX Data
Enable
(DLS1)
Length
Empty
Status
RCVR
Select
Bit (0)
Reset
(RTS)
FIFO
Send
Data
Bit 1
Bit 1
TBR
Bit 1
to
1
BIT NUMBER
Loopback
- 46 -
Stop Bits
RX Data
(EUSRI)
Interrupt
TX Data
(MSBE)
Interrupt
Multiple
Enable
Enable
Status
Bit (1)
Reset
XMIT
FIFO
Input
USR
Bit 2
Bit 2
RI
2
W83L517D/W83L517D-F
RX Data
TX Data
Interrupt
(EHSRI)
Interrupt
Bit (2)**
Enable
Enable
Enable
Status
Select
(PBE)
Mode
Parity
DMA
HSR
Bit 3
Bit 3
IRQ
Bit
3
Reserved Reversed
Internal
Loopba
Enable
Enable
(EPE)
Parity
Even
Data
Data
Bit 4
Bit 4
RX
TX
ck
4
0
0
Enable
PBFE)
Parity
Fixed
Data
Data
Bit 5
Bit 5
RX
TX
Bit
5
0
0
0
RX Data
Interrupt
TX Data
Enabled
Silence
Enable
FIFOs
Active
(SSE)
(LSB)
Level
Bit 6
Bit 6
Set
RX
**
6
0
0
RX Data
Baudrate
(BDLAB)
Interrupt
TX Data
Enabled
Access
Divisor
FIFOs
(MSB)
Active
Latch
Level
Bit 7
Bit 7
RX
Bit
**
7
0
0