ata6616 ATMEL Corporation, ata6616 Datasheet - Page 197

• Manufacturer Part Number: ata6616
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

9132A–AUTO–10/08
DRAFT
Re-synchronization in LIN Mode
When waiting for Rx Header, LBT[5..0] = 32 in LINBTR register. The re-synchronization begins
when the BREAK is detected. If the BREAK size is not in the range (10.5 bits min., 28 bits max.
— 13 bits nominal), the BREAK is refused. The re-synchronization is done by adjusting
LBT[5..0] value to the SYNCH field of the received header (0x55). Then the PROTECTED IDEN-
TIFIER is sampled using the new value of LBT[5..0]. The re-synchronization implemented in the
controller tolerates a clock deviation of ± 20% and adjusts the baud rate in a ± 2% range.
The new LBT[5..0] value will be used up to the end of the response. Then, the LBT[5..0] will be
reset to 32 for the next header.
The LINBTR register can be used to (software) re-calibrate the clock oscillator.
The re-synchronization is not performed if the LIN node is enabled as a master.
Handling LBT[5..0]
LDISR bit of LINBTR register is used to:
Note that the LENA bit of LINCR register is important for this handling (see
197).
Figure 4-75. Handling LBT[5..0]
• Disable the re-synchronization (for instance in the case of LIN MASTER node),
• To enable the setting of LBT[5..0] (to manually adjust the baud rate especially in the case of
UART mode). A minimum of 8 is required for LBT[5..0] due to the sampling operation.
=1
Write in LINBTR register
(LINCR bit 4)
LENA ?
Enable re-synch. in LIN mode
LBT[5..0] forced to 0x20
LDISR forced to 0
ATA6616/ATA6617 [Preliminary]
=0
LDISR
to write
=0
=1
Disable re-synch. in LIN mode
LBT[5..0] = LBT[5..0] to write
LDISR forced to 1
(LBT[5..0]
min
=8)
Figure 4-75 on page
197