ata6616 ATMEL Corporation, ata6616 Datasheet - Page 41

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ata6616

Manufacturer Part Number
ata6616
Description
Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
Manufacturer
ATMEL Corporation
Datasheet

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4.4.2.1
4.4.3
9132A–AUTO–10/08
DRAFT
EEPROM Data Memory
Data Memory Access Times
Figure 4-8.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 4-9.
The ATtiny167 contains EEPROM memory (see “E2 size” in
nized as a separate data space, in which single bytes can be read and written. The EEPROM
has an endurance of at least 100,000 write/erase cycles in automotive range. The access
between the EEPROM and the CPU is described in the following, specifying the EEPROM
Address Registers, the EEPROM Data Register and the EEPROM Control Register.
Section 4.22 “Memory Programming” on page 250
programming in SPI or Parallel Programming mode.
Address
clk
Data Memory Map
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
RD
Compute Address
64 I/O Registers
160 Ext I/O Reg.
T1
Memory Access Instruction
ATA6616/ATA6617 [Preliminary]
Internal SRAM
Data Memory
(ISRAM size)
32 Registers
Address valid
0x0000 - 0x001F
ISRAM start
ISRAM end
0x0020 - 0x005F
0x0060 - 0x00FF
CPU
contains a detailed description on EEPROM
T2
cycles as described in
Table 4-2 on page
Next Instruction
T3
Figure
39). It is orga-
4-9.
41

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