sta015t STMicroelectronics, sta015t Datasheet - Page 26

• Manufacturer Part Number: sta015t
• Description: Mpeg 2.5 Layer Iii Audio Decoder With Adpcm Capability
• Manufacturer: STMicroelectronics

STA015-STA015B-STA015T
PCMCROSS
Address: 0x56 (86)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The default configuration for this register is ’0x00’.
MFSDF (X)
Address: 0x61 (97)
Type: R/W
Software Reset: 0x07
Hardware Reset: 0x07
The register contains the values for PLL X divider
(see Fig. 7).
The value is changed by the internal STA015
Core, to set the clocks frequencies, according to
the incoming bitstream. This value can be even
set by the user to select the PCM interface con-
figuration.
The VCO output frequency is divided by (X+1).
This register is a reference for 32KHz and 48 KHz
input bitstream.
DAC_CLK_MODE (99)
Address: 0x63
Type: RW
Software Reset: 0x00
Hardware Reset: 0x00
This register is used to select the operating mode
for OCLK clock signal. If it is set to ’1’, the OCLK
frequency is fixed, and it is mantained to the
value fixed by the user even if the sampling fre-
quency of the incoming bitstream changes. It the
MODE flag is set to ’0’, the OCLK frequency
changes, and can be set to (512, 384, 256) * Fs.
The default configuration for this mode is 256 *
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MSB
MSB
MSB
b7
b7
b7
X
X
X
X
X
X
b6
b6
X
X
b6
X
X
X
X
b5
b5
X
X
b5
X
X
X
X
M4
b4
b4
X
b4
X
X
X
X
M3
b3
b3
X
b3
X
X
X
X
M2
b2
b2
X
b2
X
X
X
X
M1
b1
b1
X
MODE
b1
LSB
LSB
0
1
1
0
M0
b0
b0
LSB
b0
1
0
1
0
Fs. When this mode is selected, the default
OCLK frequency is 12.288 MHz.
PLLFRAC_L ([7:0])
PLLFRAC_H ([15:8])
Address: 0x64 - 0x65 (100 - 101)
Type: R/W
Software Reset: 0x46 | 0x5B
Hardware Reset: 0xNA | 0x5B
The registers are considered logically concate-
nated and contain the fractional values for the
PLL, used to select the internal configuration.
After Reset, the values are NA, and the opera-
tional setting are done when the MPEG synchro-
nisation is achieved.
The following formula describes the relationships
among all the STA015 fractional PLL parameters:
where:
FRAC=256 x FRAC_H + FRAC_L (decimal)
These registers are a reference for 48 / 24 / 12 /
32 / 16 / 8KHz audio.
PF15 PF14 PF13 PF12 PF11 PF10
MSB
MSB
PF7
b7
b7
Left channel is mapped on the left output.
Right channel is mapped on the Right output
Left channel is duplicated on both Output channels.
Right channel is duplicated on both Output channels
Right and Left channels are toggled
OCLK_Freq =
PF6
b6
b6
PF5
b5
b5
X
1
+ 1
PF4
b4
b4
Description
MCLK_freq
N + 1
PF3
b3
b3
PF2
b2
b2
M + 1 +
PF1
PF9
b1
b1
FRAC
65536
LSB
PF0
LSB
PF8
b0
b0