sta015t STMicroelectronics, sta015t Datasheet - Page 32

• Manufacturer Part Number: sta015t
• Description: Mpeg 2.5 Layer Iii Audio Decoder With Adpcm Capability
• Manufacturer: STMicroelectronics

STA015-STA015B-STA015T
GPSO_CONF
Address: 0xBA (186)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
ADC_ENABLE
Address: 0xBB (187)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
This register controls if the ADPCM data to be
encoded comes from AD interface or from MP3
bitstream input interface.
If ADCEN bit is set data to be encoded comes
from ADC interface, otherwise data comes from
MP3 stream interface
32/44
MSB
MSB
GSP:
GRP:
b7
b7
X
X
b6
b6
X
X
GPSO Sclk polarity
Using this bit the GPSO_SCLK polarity can
be controlled. Clearing GSP bit data on
GPSO_DATA line will be provided on the
rising edge of GPSO_SCLK (sampling on
falling edge). Setting GSP bit data are
provided on falling edge of GPSO_SCLK
(sampling on rising edge)
GPSO Request Polarity
This bit is used to determine the polarity of
GPSO_REQ signal. If GRP bit is cleared
data are valid on GPSO_REQ signal high. If
this bit is set data are valid on GPSO_REQ
signal low
b5
X
b5
X
b4
X
b4
X
b3
X
b3
X
b2
X
b2
X
GRP
b1
b1
X
ADCEN
LSB
GSP
LSB
b0
b0
ADC_CONF
Address: 0xBC (188)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
Using this register the ADC input interface can be
configured as follow:
MSB
ALRCP:
ALRCS:
LRCK
DATA
ALRCP ALRCS
b7
ASCP:
X
ADC:
AIIS:
0
1
0
1
b6
X
DATA 0
ADC I2S mode
0 =
1 =
ADC Data Config.
0 =
1 =
ADC Serial Clock Polarity
0 =
1 =
ADC Left/Right Clock Polarity
ADC Left/Right Clock Start value this two
bits permit to determine Left/Right clock
usage according to the following table:
b5
X
0
0
1
1
DATA 1
sample word must be aligned with
LRCK (no I
sample word not aligned with LRCK
(I
sample word is LSB first
sample word is MSB first
Data is sampled on rising edge
Data is sampled an falling edge
ALRCS ALRCP ASCP ADC AIIS
2
S compliant mode)
b4
(Data1, Data2)
(0, 1)
(0, 1)
(1, 2)
LEFT/RIGHT COUPLE
DATA 2
2
b3
S mode)
DATA 3
b2
D99AU1065
(Data3, Data4)
DATA 4
(2, 3)
(2, 3)
(3, 4)
b1
LSB
b0