sta015t STMicroelectronics, sta015t Datasheet - Page 31

• Manufacturer Part Number: sta015t
• Description: Mpeg 2.5 Layer Iii Audio Decoder With Adpcm Capability
• Manufacturer: STMicroelectronics

ANCILLARY DATA BUFFER
Address: 0x7E - 0xB5 (126 - 181)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
STA015 can extract max 56 bytes/MPEG frame.
To know the number of A.D. bits available every
MPEG frame, the ANCCOUNT_L and ANC-
COUNT_H registers (0x41 and 0x42) have to be
read.
The buffer dimension is 5 bytes, written by
STA015 core in sequential order. So the whole
set of ancillary data may be accessed in one
shot. The timing information to read the buffer
can be obtained by reading the FRAME_CNT
registers (0x67 - 0x69).
ISR
Address: 0xB6 (182)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
X = don’t care;
0 = no ancillary data
1 = Ancillary Data Available
The ISR is used by the microcontroller to under-
stand when a new ancillary data block is avail-
able.
ADPCM_CONFIG
Address: 0xB8 (184)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB
b7
X
b6
X
b5
X
b4
X
b3
X
b2
X
b1
X
LSB
b0
0
1
This register controls ADPCM engine and how
data must be compressed.
GPSO_ENABLE
Address: 0xB9 (185)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
This register enable/disable the GPSO interface.
Setting the GEN bit will enable the serial interface
for ADPCM data retrieving. Reset GEN bit to dis-
able GPSO interface.
MSB
ASM_EN: ADPCM Stereo Mode Enable
AA0,AA1: ADPCM Algorithm selection
AFM_EN ADPCM Frame Mode Enable
MSB
b7
X
b7
X
AA1
0
0
1
1
b6
X
b6
X
0 =
1 =
0 =
1 =
The ADPCM encoding/decoding algorithm
can be selected according to the following
table:
b5
X
AA0
b5
X
0
1
0
1
STA015-STA015B-STA015T
b4
no frames (raw formed)
select the framed output formate for
ADPCM encoded data
Disable stereo mode
Enable stereo mode
X
b4
X
AA1 AA0 ASM_EN AFM_EN
b3
G723-24 algorithm (24kbp/s)
G723-40 algorithm (40kbp/s)
G721 algorithm (32kbp/s)
b3
X
b2
DVI algorithm
b2
X
b1
b1
X
LSB
b0
GEN
LSB
31/44
b0