sta335bw STMicroelectronics, sta335bw Datasheet - Page 23

• Manufacturer Part Number: sta335bw
• Description: 2.1 Channels High Efficiency Digital Audio System
• Manufacturer: STMicroelectronics

STA335BW
5.2.4
5.2.5
Table 11.
Delay serial clock enable
Channel input mapping
Each channel received via I
Channel Input Mapping registers. This allows for flexibility in processing. The default
settings of these registers map each I
channel.
Bit
Bit
5
6
7
BICKI
64fs
R/W
R/W
R/W
R/W
R/W
Supported serial audio input formats for LSB-first (SAIFB = 1) (continued)
RST
RST
0
0
1
SAI (3...0)
0000
0100
1000
1100
0001
0101
1001
1101
0010
0110
1010
1110
2
S can be mapped to any internal processing channel via the
DSCKE
Name
Name
C1IM
C2IM
2
S input channel to its corresponding processing
SAIFB
1
1
1
1
1
1
1
1
1
1
1
1
0 – Processing channel 1 receives Left I
1 – Processing channel 1 receives Right I
0 – Processing channel 2 receives Left I
1 – Processing channel 2 receives Right I
0 – No serial clock delay
1 – Serial clock delay by 1 core clock cycle to
tolerate anomalies in some I2S master devices
I
I
I
LSB first I
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
2
2
2
S 24-bit data
S 20-bit data
S 18-bit data
2
S 16-bit data
Interface Format
Description
Description
Register description
2
2
S Input
S Input
2
2
S Input
S Input
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