at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 133

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

“Autoswitch” Mode
IN Pipe management
“Manual” Mode
7632D–MP3–01/07
Example with 1 IN data bank
Example with 2 IN data banks
RXIN
RXIN
FIFOCON
FIFOCON
IN
IN
(to bank 0)
(to bank 0)
DATA
DATA
HW
HW
ACK
ACK
In this mode, the clear of the FIFOCON bit is performed automatically by hardware each
time the Pipe bank is full. The firmware has to check if the next bank is empty or not
before writing the next data. On TXOUT interrupt, the firmware fills a complete bank. A
new interrupt will be generated each time the current bank becomes free.
The Pipe must be configured first.
When the Host requires data from the device, the firmware has to determine first the IN
mode to use using the INMODE bit:
•
•
The IN request generation will start when the firmware clear the PFREEZE bit.
Each time the current bank is full, the RXIN and the FIFOCON bits are set. This triggers
an interrupt if the RXINE bit is set. The firmware can acknowledge the USB interrupt by
clearing the RXIN bit. The Firmware read the data and clear the FIFOCON bit in order to
free the current bank. If the IN Pipe is composed of multiple banks, clearing the FIFO-
CON bit will switch to the next bank. The RXIN and FIFOCON bits are then updated by
hardware in accordance with the status of the new bank.
INMODE = 0. The INRQX register is taken in account. The Host controller will
perform (INRQX+1) IN requests on the selected Pipe before freezing the Pipe. This
mode avoids to have extra IN requests on a Pipe.
INMODE = 1. The USB controller will perform infinite IN request until the firmware
freezes the Pipe.
SW
SW
read data from CPU
read data from CPU
IN
BANK 0
BANK 0
(to bank 1)
DATA
SW
SW
IN
HW
ACK
(to bank 0)
read data from CPU
SW
DATA
BANK 1
HW
ACK
SW
read data from CPU
BANK 0
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