at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 231

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

OverRun Condition
Interrupt
Registers
7632D–MP3–01/07
This error means that the speed is not adapted for the running application.
An OverRun condition occurs when a byte has been received whereas the previous one
has not been read by the application yet.
The last byte (which generate the overrun error) does not overwrite the unread data so
that it can still be read. Therefore, an overrun error always indicates the loss of data.
The SPI handles 3 interrupt sources that are the “end of transfer”, the “mode fault” and
the “transmit register empty” flags.
As shown in Figure 125, these flags are combined together to appear as a single inter-
rupt source for the C51 core.
The SPIF flag is set at the end of an 8-bit shift in and out and is cleared by reading
SPSCR and then reading from or writing to SPDAT.
The MODF flag is set in case of mode fault error and is cleared by reading SPSCR and
then writing to SPCON.
The SPTE flag is set when the transmit register is empty and ready to receive new data.
When SPTE interrupt source is enabled, SPIF flag does not generate any interrupt.
The SPI interrupt is enabled by setting ESPI bit in IEN1 register. This assumes inter-
rupts are globally enabled by setting EA bit in IEN0 register.
Figure 125. SPI Interrupt System
Table 252. SPCON Register
SPCON (1:91h) – SPI Control Register
Number
SPR2
Bit
7
7
6
5
SPSCR.7
SPSCR.3
SPSCR.4
MODF
SPTE
SPIF
Mnemonic Description
SSDIS
SPEN
SPEN
SPR2
Bit
6
MODFIE
SPTEIE
SPSCR.1
SPSCR.0
SPI Rate Bit 2
Refer to Table 251 for bit rate description.
SPI Enable Bit
Set to enable the SPI interface.
Clear to disable the SPI interface.
Slave Select Input Disable Bit
Set to disable SS in both master and slave modes. In slave mode this bit has no
effect if CPHA = 0.
Clear to enable SS in both master and slave modes.
SSDIS
5
MSTR
4
CPOL
3
IEN1.3
ESPI
CPHA
2
SPI Controller
Interrupt Request
SPR1
1
SPR0
0
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