at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 201

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Figure 94. Data Block Reception Flows
Card Management
Card Detect Input
Card Lock Input
7632D–MP3–01/07
read 8 data from MMDAT
a. Polling mode
Start Transmission
FIFO Reading
No More Data
Data Block
To Receive?
Reception
DATEN = 1
FIFO Full?
HFRS = 1?
As shown in Figure 95 the SDINS (MMC/SD Card Detect) input implements an internal
pull-up, in order to provide static high level when card is not present in the socket.
SDINS level is reported by CDET bit
As soon as MMC controller is enabled, all level modifications on SDINS input from H to
L or from L to H (card insertion or removal) set CDETI, the Card Detect Interrupt flag in
MMINT (see Table 227).
Note:
Figure 95. Card Detection Input Block Diagram
As shown in Figure 96 the SDLCK (SD Lock) input implements an internal pull-up, in
order to provide static high level when card is not present in the socket.
SDLCK level is reported by SDWP bit
Note:
1. CDET bit is not relevant until MMC controller is enabled (MMCEN = 1).
1. SDWP bit is not relevant until MMC controller is enabled (MMCEN = 1) and a card is
SDINS
present in the socket (CDET = 0).
IOVDD
Unmask FIFO Full
Start Reception
R
Initialization
Data Block
PU
DATEN = 1
HFRM = 0
MMSTA.6
CDET
(1)
(1)
in MMSTA.
b. Interrupt mode
in MMSTA register.
read 8 data from MMDAT
Reception ISR
Mask FIFO Full
FIFO Reading
No More Data
Data Block
To Receive?
FIFO Full?
HFRI = 1?
HFRM = 1
MMINT.7
CDETI
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