at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 225

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Description
Master Mode
7632D–MP3–01/07
Figure 115. Typical Slave SPI Bus Configuration
The SPI controller interfaces with the C51 core through three special function registers:
SPCON, the SPI control register (see Table 252); SPSCR, the SPI status and control
register (see Table 253); and SPDAT, the SPI data register (see Table 254).
Data flow transfer can be fully handled by the C51 by writing and reading SPDAT or par-
tially by the C51 and the DFC. The SPI controller implements only one DFC channel,
meaning only reception flow or transmission flow can be handled by the DFC at a time.
The Figure 116 summarizes the different data flow configuration allowed.
Figure 116. SPI Data Flow Configurations
The SPI operates in master mode when the MSTR bit in SPCON is set.
Note:
Figure 117 shows the SPI block diagram in master mode. Only a master SPI module
can initiate transmissions.
•
•
•
MASTER
Data flow is fully handled by
the CPU.
Peripheral X is configured as
source and SPI as destination
of a DFC channel. CPU is still
able to read incoming data
(usually status) at its own rate.
Peripheral X is configured as
destination and SPI as source
of a DFC channel. CPU is still
able to output data (usually
status) at its own rate.
The SPI Module should be configured as a master before it is enabled (SPEN set). In a
system, the master SPI should be configured before the slave SPI device.
MISO
MOSI
SCK
SSn
SS1
SS0
SS
SO
Slave 1
SI
SCK
Per X
Per X
Per X
SS
SO
Slave 2
SI
SCK
DFC
DFC
DFC
CPU
CPU
CPU
SPI
SPI
SPI
MISO MOSI SCK
SS
AT85C51SND3B
Slave
IN
OUT
IN
OUT
IN
OUT
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