at85c51snd3 ATMEL Corporation, at85c51snd3 Datasheet - Page 170

• Manufacturer Part Number: at85c51snd3
• Description: At85c51snd3 Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Clock Unit
Control Unit
Configuration Descriptor
170
AT85C51SND3B
Figure 79. Nand Flash Connection
The NFC clock is generated based on the clock generator as detailed in Section
"DFC/NFC Clock Generator", page 31. As soon as NFEN bit in NFCON is set, the NFC
controller receives its system clock and can then be configured.
The Control unit configures the NFC and gives the user all the flexibility to interface the
NF devices. All the flash commands must be produced by the software, and the NFC
just sends to the Flash basic operations such as “read Id”, “write a byte”, “erase a
block”, …
Prior to any operation, the NFC must be configured with static information concerning
the NF devices connected to the product as well as other important information relevant
to the desired behavior. The configuration is done by writing a descriptor byte by byte in
the NFCFG register. The NF descriptor is composed of eight bytes (detailed in
Table 189). The first byte written is byte 0.
After writing a descriptor, a new one can be written to the NFC.
Table 189. Configuration Descriptor Content
Offset
Byte
0
1
2
3
4
5
6
7
NFCE3:0
NFD7:0
NFCLE
NFALE
IOVDD
IOVSS
NFWE
NFWP
NFRE
SMPGCFG
Mnemonic
NFPGCFG
SCFG1
SCFG2
FPBH
LPBH
FPBL
LPBL
Byte
Description
NF Device Page Configuration Register
Refer to Table 190 for register content organization.
SMC Device Page Configuration Register
Refer to Table 190 for register content organization.
Sub Configuration Register 1
Refer to Table 191 for register content organization.
Sub Configuration Register 2
Refer to Table 192 for register content organization.
NF Device First Protected Block Address Registers
First address block of protected area. Refer to Section “Write Protection” for
detailed information.
Reset Value is 0000 0000b, 0000 0000b.
NF Device Last Protected Block Address Registers
First address block of protected area. Refer to Section “Write Protection” for
detailed information.
Reset Value is 0000 0000b, 0000 0000b.
CLE
ALE
WE
RE
D7:0
WP
CE
0
NF0
VDD
VSS
CLE
ALE
WE
RE
D7:0
WP
CE
1
NF1
VDD
VSS
CLE
ALE
WE
RE
D7:0
WP
CE
2
NF2
VDD
VSS
CLE
ALE
WE
RE
D7:0
WP
7632D–MP3–01/07
CE
3
SMC
NF3
VDD
VSS