saa6713h NXP Semiconductors, saa6713h Datasheet - Page 18

• Manufacturer Part Number: saa6713h
• Description: Xga Dual Input Flat Panel Controller
• Manufacturer: NXP Semiconductors

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Table 9 Mode detection configuration registers (page 2); note 1
Note
1. X = don’t care.
Mode detection: 00H to 0EH
MD_CTRL
MD_INT_EN
MD_POL
MD_V_LINE_HI
MD_V_LINE_LO
MD_H_CLK_HI
MD_H_CLK_LO
MD_V_CLK_HI
MD_V_CLK_MD
MD_V_CLK_LO
MD_INT_HI
MD_INT_LO
MD_ACT_INT
MD_SYNC_ACT
MD_ACT_IEN
DVI enhancements: 20H to 21H
DVI_FILTER_0
DVI_FILTER_1
REGISTER
00H W
ADR R/W
01H W
02H R
03H R
04H R
05H R
06H R
07H R
08H R
09H R
0AH R
0BH R
0CH R
0DH R
0EH W
20H W
21H W
0000 0000 jitter_int_en v_lines_
00H
00H
00H
00H
00H
00H
X000 0000 delock_int
0000 0000 delock_int_
00H
00H
000 0000
RESET
00 0000
00 0000
0 0011
000
000
v_lines[7:0]
h_clocks[15:8]
h_clocks[7:0]
v_clocks[23:16]
v_clocks[15:8]
v_clocks[7:0]
en
dvi_filter[7:0] recommended value FDH
dvi_filter[7:0] recommended value 3FH
D7
no_vsync_
int_en
int_en
reserved
reserved
D6
clear_int
v_clocks_
int_en
vsync_int
dvs_act_int dhs_act_int asog_act_
dvs_active dhs_active asog_
dvs_int_en dhs_int_en asog_int_
D5
int_lock
h_clocks_
int_en
jitter_
detected
jitter_int
D4
delay_
vsync
no_hsync_
int_en
vsync_pol
vsync_pol_
int
int
active
en
D3
h_clocks_
accu
vsync_int_
en
hsync_pol
v_lines[10:8]
hsync_pol_
int
v_lines_int h_clocks_
acsvs_act_
int
acsvs_
active
acsvs_int_
en
D2
h_clocks_
cont
vsync_pol_
int_en
no_vsync
no_vsync_
int
int
avs_act_int ahs_act_int
avs_active ahs_active
avs_int_en ahs_int_en
D1
md_on
hsync_pol_
int_en
no_hsync
no_hsync_
int
v_clocks_
int
D0