saa6713h NXP Semiconductors, saa6713h Datasheet - Page 49

• Manufacturer Part Number: saa6713h
• Description: Xga Dual Input Flat Panel Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.8
The Digital Visual Interface (DVI) provides a high-speed
digital connection for visual data types that is display
technology independent. The interface is primarily focused
at providing a connection between a computer and its
display device.
The DVI uses a communications protocol called Transition
Minimized Differential Signalling (TMDS )
protocol uses a digital encoding and decoding algorithm to
minimize the number of transitions (from HIGH-to-LOW or
vice-versa) within a packet of bits, thereby lowering the
energy in the electromagnetic spectrum that the system
radiates. Using TMDS , it is generally easier to meet
ElectroMagnetic Compatibility (EMC) requirements.
The TMDS
10-bit frames (TMDS
channel it recovers and decodes these frames into either
8-bit words or two control bits. It also decodes a Data
Enable (DE) signal that indicates when the receiver is
receiving active data and when it is receiving control data.
The clock indicates the frequency of one TMDS
packet, i.e. the clock frequency is one tenth of the bit rate.
The DVI interface is automatically enabled when selected
as input source for the input interface.
(1) Transition Minimized Differential Signalling (TMDS) is a
Table 29 HDCP registers on the Display Data Channel (DDC) I
2004 Apr 05
DDC_HDCP_BKSV0
DDC_HDCP_BKSV1
DDC_HDCP_BKSV2
DDC_HDCP_BKSV3
DDC_HDCP_BKSV4
Reserved
DDC_HDCP_RI0
DDC_HDCP_RI1
Reserved
DDC_HDCP_AKSV0
DDC_HDCP_AKSV1
DDC_HDCP_AKSV2
DDC_HDCP_AKSV3
DDC_HDCP_AKSV4
Reserved
XGA dual input flat panel controller
subset of PanelLink technology which is a registered
trademark of Silicon Image, Inc.
DVI interface
REGISTER
receiver inputs are three data streams of
data) and one clock channel. Per
00H
01H
02H
03H
04H
05H to 07H
08H
09H
0AH to 0FH
10H
11H
12H
13H
14H
15H to 17H
ADDRESS
(1)
R
R
R
R
R
R
R
W
W
W
W
W
. This
R/W
data
X
X
X
X
X
00H
X
X
00H
X
X
X
X
X
00H
RESET
49
7.8.1
The DVI interface becomes High-bandwidth Digital
Content Protection (HDCP) version 1.0 compliant.
Authentication in hardware is supported. Therefore, the
SAA6713H offers two signals: HSCL and HSDA. They are
the clock and the data signal for the Device Data Channel
(DDC) I
process.The HDCP keys are stored in an on-chip SRAM.
The system microcontroller is supposed to transfer them
from its ROM during initialization phase. No external
EEPROM for key storage is required. The HDCP registers
are mapped in Table 29.
The HDCP related internal configuration registers are
placed on page 1 and the bits are mapped in Table 30.
Moreover, a dedicated software reset for the HDCP circuit
together with the DVI receiver is introduced.
hdcp_bksv[7:0], receiver key selection vector
hdcp_bksv[15:8]
hdcp_bksv[23:16]
hdcp_bksv[31:24]
hdcp_bksv[39:32]
hdcp_ri[7:0], link verification response
hdcp_ri[15:8]
hdcp_aksv[7:0], transmitter key selection vector
hdcp_aksv[15:8]
hdcp_aksv[23:16]
hdcp_aksv[31:24]
hdcp_aksv[39:32]
2
C-bus; notes 1 and 2
2
C-bus that is used in the authentication
HDCP
FIELDS
Product specification
SAA6713H