tda5251f1 Infineon Technologies Corporation, tda5251f1 Datasheet - Page 23

• Manufacturer Part Number: tda5251f1
• Description: Ask/fsk 315mhz Wireless Transceiver
• Manufacturer: Infineon Technologies Corporation

Confidential
The I
parameters at any time.
It is possible to set the device in three different modes: Slave Mode, Self Polling Mode and Timer
Mode. This is done by a state machine which is implemented in the WAKEUP LOGIC unit. A
detailed description is given in Section 2.4.16.
The DATA VALID DETECTOR contains a frequency window counter and an RSSI threshold
comparator. The window counter uses the incoming data signal from the data slicer as the gating
signal and the crystal oscillator frequency as the timebase to determine the actual datarate. The
result is compared with the expected datarate.
The threshold comparator compares the actual RSSI level with the expected RSSI level.
If both conditions are true the PwdDD pin is set to LOW in self polling mode as you can see in
Section 2.4.16. This signal can be used as an interrupt for an external µP. Because the PwdDD
pin is bidirectional and open drain driven by an internal pull-up resistor it is possible to apply an
external LOW thus enabling the device.
2.4.15
The TDA5251 supports the I
selectable by the BusMode pin (pin 2) as shown in the following table. All bus pins (BusData,
BusCLK, EN, BusMode) have a Schmitt-triggered input stage. The BusData pin is bidirectional
where the output is open drain driven by an internal 15kW pull up resistor.
Table 2-6
Figure 2-7
Note: The Interface is able to access the internal registers at any time, even in POWER DOWN
mode. There is no internal clock necessary for Interface operation.
Preliminary Specification
3-wire Mode
2
Function
I
2
C / 3-wire Bus Interface gives an external microcontroller full control over important system
C Mode
Bus Interface and Register Definition
Bus Interface Format
Bus Interface
BusMode
High
Low
BusMode
BusData
BusCLK
2
C bus protocol (2 wire) and a 3-wire bus protocol. Operation is
EN
16
17
24
2
High= inactive,
Low= active
EN
23
1 1 1 0 0 0 0 0
INTERFACE
CHIP ADDRESS
I
2
C / 3-wire
INTERNAL BUS
Clock input
BusCLK
Functional Description
Data in/out
TDA5251 F1
BusData
Version 1.0
2003-02-18
i2c_3w_bus.wmf