tda5251f1 Infineon Technologies Corporation, tda5251f1 Datasheet - Page 33

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tda5251f1

Manufacturer Part Number
tda5251f1
Description
Ask/fsk 315mhz Wireless Transceiver
Manufacturer
Infineon Technologies Corporation
Datasheet
Confidential
With default settings the clock generating units are disabled during PD, therefore no clock is
available at the clock output pin. It is possible to offer a clock signal at the clock output pin every
time (also during PD) if the CLK_EN Bit in the CONFIG register is set to HIGH.
Figure 2-15
Note: The time values are typical values
Figure 2-16
*
Note: The time values are typical values
Preliminary Specification
State is either „I“ or „O“ depending on time of setting into powerdown
DC OFFSET COMPENSATION
PEAK DETECTOR EN
DATADETECTION EN
DC OFFSET COMPENSATION
POWER AMP EN
PEAK DETECTOR EN
DATADETECTION EN
XTAL EN
STATUS
POWER AMP EN
0.5ms
t
C LK S U
1
1st start or reset in PD mode
st
XTAL EN
STATUS
start or reset in active mode
0.5ms
t
C L KS U
RESET
or 1
PWDDD = low
TX activ or RX activ
st
POWER ON
RESET
or 1
PWDDD = high
CLOCK FOR EXTERNAL µP
t
S Y S S U
8ms
st
POWER ON
CLOCK FOR EXTERNAL µP
1.1ms
t
T X S U
PD
if RX
if RX
if RX
if TX
t
2.2ms
t
2.6ms
R X S U
D D S U
t
0.5ms
C LK S U
PWDDD = low
33
PD
*
TX activ or RX activ
t
S Y S S U
8ms
TX activ
1.1ms
t
TX S U
t
1.1ms
TX S U
if RX
t
0.5ms
C L K S U
PD
*
if RX
if RX
if TX
t
2.2ms
t
2.6ms
R X SU
D D S U
RX activ
0.5ms
t
C LK S U
Functional Description
PD
*
t
2.2ms
t
2.6ms
R X S U
D D S U
TX activ
TX activ
t
Sequenzer_Timing_pupstart.wmf
t
1.1ms
1.1ms
TX S U
TX S U
Sequenzer_Timing_pdstart.wmf
TDA5251 F1
RX activ
Version 1.0
RX activ
t
2.2ms
t
2.6ms
R X S U
D D S U
2003-02-18
t
2.2ms
t
2.6ms
R X S U
D D S U

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