tda5251f1 Infineon Technologies Corporation, tda5251f1 Datasheet - Page 35

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tda5251f1

Manufacturer Part Number
tda5251f1
Description
Ask/fsk 315mhz Wireless Transceiver
Manufacturer
Infineon Technologies Corporation
Datasheet
Confidential
Table 2-29
Note: Data are valid 500 µs after the crystal oscillator is enabled (see Figure 2-15 and Figure 2-
16, t CLKSU ).
Table 2-30
Note: As long as default settings are used, there is no clock available at the clock output during
Power Down. It is possible to enable the clock during Power Down by setting CLK_EN (Bit D9) in
the Config Register (00H) to HIGH.
2.4.20
The input of the 6Bit-ADC can be switched between two different sources: the RSSI voltage (default
setting) or a resistor network dividing the Vcc voltage by 5.
Table 2-31
Preliminary Specification
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SELECT
D5
0
0
1
1
0
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RSSI and Supply Voltage Measurement
CLK_DIV Output Selection
CLK_DIV Setting
Source for 6Bit-ADC Selection (Register 08H)
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D4
0
1
0
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Total Divider Ratio
Input for 6Bit-ADC
RSSI (default)
Vcc / 5
10
12
14
16
18
20
22
24
26
28
30
32
2
4
6
8
Output from Divider (default)
35
Window Count Complete
13.125MHz
Output
32kHz
Output Frequency [MHz]
0.730 (default)
0.,55
0.94
0.82
0.47
0.44
0.41
Functional Description
0.66
3.3
2.2
1.6
1.3
1.1
0.6
0.5
6.6
TDA5251 F1
Version 1.0
2003-02-18

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