px1011b NXP Semiconductors, px1011b Datasheet - Page 8

• Manufacturer Part Number: px1011b
• Description: Pci Express Stand-alone X1 Phy Semiconductors
• Manufacturer: NXP Semiconductors

NXP Semiconductors
8. Functional description
PX1011B_2
Product data sheet
8.1 Receiving data
Table 11.
The main function of the PHY is to convert digital data into electrical signals and vice
versa. The PCI Express PHY handles the low level PCI Express protocol and signaling.
The PX1011B PCI Express PHY consists of the Physical Coding Sub-layer (PCS), a
Serializer and De-serializer (SerDes) and a set of I/Os (pads). The PCI Express PHY
handles the low level PCI Express protocol and signaling. This includes features such as
Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding,
analog buffers, elastic buffer and receiver detection.
The PXPIPE interface between the MAC and PX1011B is a superset of the PHY Interface
for the PCI Express (PIPE) specification. The following feature have been added:
The 8-bit data width PXPIPE interface operates at 250 MHz with SSTL_2 class I
signaling. PX1011B does not integrate SSTL_2 termination resistors inside the IC.
The PCI Express link consists of a differential input pair and a differential output pair. The
data rate of these signals is 2.5 Gbit/s.
Incoming data enters the chip at the RX interface. The receiver converts these signals
from small amplitude differential signals into rail-to-rail digital signals. The carrier detect
circuit detects whether data is present on the line and passes this information through to
the SerDes and PCS.
If a valid stream of data is present the Clock and Data Recovery unit (CDR) first recovers
the clock from the data and then uses this clock for re-timing the data (i.e., recovering the
data).
Symbol
V
V
V
V
V
V
V
•
DDA1
DDA2
DDD1
DDD2
DDD3
DD
SS
Source synchronous clocks for RX and TX data to simplify timing closure.
Pin
D5
D4
E3, E5
C3, C5, C7, E7,
G5, G7
E6, F5, F6
D3
A1, B2, B5, B8,
C2, C4, C6, D1,
D2, D7, E2, E8,
F2, F7, G1, G2,
G4, G6, H2, H5,
H8
PCI Express PHY power supplies
Rev. 02 — 19 March 2008
Type
power
power
power
power
power
power
ground
Signaling
Description
1.2 V analog power supply for serializer and
de-serializer
3.3 V analog power supply for serializer and
de-serializer
3.3 V power supply for JTAG I/O
2.5 V power supply for SSTL_2 I/O
1.2 V power supply for core
1.2 V power supply for high-speed serial
PCI Express I/O pads and PVT
ground
PCI Express stand-alone X1 PHY
PX1011B
© NXP B.V. 2008. All rights reserved.
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