w83877atd Winbond Electronics Corp America, w83877atd Datasheet - Page 138

• Manufacturer Part Number: w83877atd
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

Bit 3 :ENBNKSEL - Bank select enable
Bit 2 :CLKINSEL - Clock input selection
Bit 1, Bit 0: Reserved
8.2.37 Configuration Registers (CR2D)
When the device is in Extended Function mode and EFIR is 2D
accessed through EFDR. This register default value is 00
This register controls the data rate selection for FDC. It also controls if precompensation is enabled.
DRTA1, DRTA0 (bit 1 - bit 0):
These two bits combining with data rate selection bits in Date Rate Register select the operational
data rate for FDD A as follows:
Drive Rate Table
DRTA1
0
0
0
0
0
0
0
0
1
1
1
1
= 0 Disable UART B bank selection
= 1 Enable UART B bank selection
= 0 The clock on pin CLKIN is 24 MHz
= 1 The clock on pin CLKIN is 48MHz
DRTA0
0
0
0
0
1
1
1
1
0
0
0
0
7
6
5
Data Rate
DRATE1
1
0
0
1
1
0
0
1
1
0
0
1
4
3
- 134 -
2
DRATE0
1
0
1
0
1
0
1
0
1
0
1
0
1
16
. The bit definitions are as follows:
0
DRTA0
DRTA1
DIS_PRECOMP0
DRTB0
DRTB1
DIS_PRECOMP1
Reserved
Reserved
Publication Release Date: April 1998
operational data rate
MFM
1M
500K
300K
250K
1M
500K
500K
250K
1M
500K
2M
250K
16
, the CR2D register can be
W83877ATF
FM
---
250K
150K
125K
---
250K
250K
125K
---
250K
---
125K
Version 0.51