w83877atd Winbond Electronics Corp America, w83877atd Datasheet - Page 60

• Manufacturer Part Number: w83877atd
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

Bit 2:
Bit 1, 0:
4.3.2.6 Set0.Reg5 - UART Status Register (USR)
Legacy UART Register: These registers are defined the same as in the previous description.
Advanced UART Register:
Bit 7:
Bit 6, 5:
Bit 4:
Bit 3:
Advanced
Reset Value
Legacy
UART
UART
Mode
MIR, FIR modes:
Other modes:
MIR, FIR modes:
MIR, FIR modes:
MIR, FIR modes:
LB_INFR
EN_DMA - Enable DMA
Enable DMA function to transmit or receive. Before using this, the DMA channel should
be select. If RX DMA channel is set and TX DMA channel is disabled, then the single
DMA channel is used. In the single channel system, the bit of D_CHSW (DMA channel
swap, in Set 2.Reg2.Bit3) will determine RX DMA channel or TX DMA channel.
Not used.
RTS, DTR
Functional definitions are the same as in legacy UART mode.
LB_INFR - Last Byte In Frame End
Set to 1 when the last byte of a frame is in the FIFO bottom. This bit indicates that one
frame is separated from another frame when RX FIFO has more than one frame.
Same as legacy UART description.
MX_LEX - Maximum Frame Length Exceed
Set to 1 when frame length from the receiver has exceeded the programmed frame
length,
any data to RX FIFO.
PHY_ERR - Physical Layer Error
Set to 1 when an illegal data symbol is received, where the illegal data symbol is defined
in physical layer of IrDA version 1.1. When this bit is set to 1, the decoder of receiver will
be
RFEI
B7
aborted,
0
which is in SET4.Reg6 and Reg5. If this bit is set to 1, the receiver will not receive
and a frame end signal is set to 1.
TSRE
TSRE
B6
0
TBRE
TBRE
B5
0
MX_LEX PHY_ERR CRC_ERR
SBD
- 56 -
B4
0
NSER
B3
0
Publication Release Date: April 1998
PBER
B2
0
W83877ATF
OER
OER
B1
0
Version 0.51
RDR
RDR
B0
0