pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 43

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 2
Pin No.
66
65
Data Sheet
Name
RL1.4
RDIP4
ROID4
RL2.4
RDIN4
RCLKI4
I/O Signals for P-TQFP-144-8 (cont’d)
Pin Type
I (analog)
I
I
I (analog)
I
I
Buffer
Type
–
–
–
–
–
–
Function
Line Receiver input 1, port 4
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
Receive Data Input Positive, port 4
Digital input for received dual-rail PCM(+) route signal which
is latched with the internally recovered receive route clock.
An internal DPLL extracts the receive route clock from the
incoming data pulses. The duty cycle of the received signal
has to be close to 50%. The dual-rail mode is selected if
LIM1.DRS and FMR0.RC1 are set. Input polarity is selected
by bit RC0.RDIS (after reset: active low), line coding is
selected by FMR0.RC(1:0).
Receive Optical Interface Data, port 4
Unipolar data received from a fiber-optical interface with
2048 kbit/s (E1) or 1544 kbit/s (T1/J1). Latching of data is
done with the falling edge of RCLKI. Input polarity is selected
by bit RC0.RDIS. The single-rail mode is selected if
LIM1.DRS is set and FMR0.RC1 is cleared. If CMI coding is
selected (FMR0.RC(1:0) = 01
clock an data; no clock signal on RCLKI4 is required.
Line Receiver input 2, port 4
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
Receive Data Input Negative, port 4
Input for received dual-rail PCM(-) route signal which is
latched with the internally recovered receive route clock. An
internal DPLL extracts the receive route clock from the
incoming data pulses. The duty cycle of the received signal
has to be close to 50%.
The dual-rail mode is selected if LIM1.DRS and FMR0.RC1
are set. Input polarity is selected by bit RC0.RDIS
(after reset: active low), line coding is selected by
FMR0.RC(1:0).
Receive Clock Input, port 4
Receive clock input for the optical interface if LIM1.DRS is
set and
FMR0.RC(1:0) = 00
Clock frequency: 2.048 MHz (E1) or 1.544 MHz (T1/J1).
RCLKI4 is ignored if CMI coding is selected.
43
B
.
B
), an internal DPLL recovers
Rev. 1.3, 2006-01-25
Pin Descriptions
QuadLIU
PEF 22504
TM