pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 58

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 2
Pin No.
4
5
6
7
4
5
6
7
4
5
6
7
4
5
6
7
14
15
16
17
22
23
24
25
Data Sheet
Name
RPA1
RPB1
RPC1
RPD1
RPA1
RPB1
RPC1
RPD1
RPA1
RPB1
RPC1
RPD1
RPA1
RPB1
RPC1
RPD1
RPA2
RPB2
RPC2
RPD2
RPA3
RPB3
RPC3
RPD3
I/O Signals for P-TQFP-144-8 (cont’d)
Pin Type
O
O
I
O
I/O
I/O
Buffer
Type
–
–
PU
–
PU/–
PU/–
Function
General Purpose Output Low (GPOL), port 1
PC(1:4).RPC(3:0) = 1011
The pin level is set fix to low level.
Loss of Signal Indication Output (LOS), port 1
PC(1:4).RPC(3:0) = 1100
The output reflects the Loss of Signal status as readable in
FRS0.LOS.
Receive TDM System Interface Tristate (RTDMT), port 1
PC(1:4).RPC(3:0) = 1101
Controlling of tristate mode for RDO, RSIG,SCLKR and
RFM. The RTDMT value is logically exored with the register
bit SIC3.RRTRI.
Receive Clock Output (RCLK), port 1
PC(1:4).RPC(3:0) = 1111
Receive clock output RCLK. After reset RCLK is configured
to be internally pulled up weekly. By setting of PC5.CRP
RCLK is an active output.
RCLK source and frequency selection is made by
CMR1.RS(1:0) if GPC6.COMP_DIS = 0
CMR4.RS(2:0) if GPC6.COMP_DIS = 1
Receive Multifunction Pins A to D, port 2
Depending on programming of bits PC(1:4).RPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadLIU
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESR latching/transmission of data is done with the
rising or falling edge of SCLKR. If not connected, an internal
pullup transistor ensures a high input level.
The input function must not be selected twice or more.
Selectable pin functions as described for port 1.
Receive Multifunction Pins A to D, port 3
Depending on programming of bits PC(1:4).RPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadLIU
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESR latching/transmission of data is done with the
rising or falling edge of SCLKR. If not connected, an internal
pullup transistor ensures a high input level.
The input function must not be selected twice or more.
Selectable pin functions as described for port 1.
58
B
B
B
B
.
.
.
. Default setting after reset
TM
TM
. After reset these ports
. After reset these ports
Rev. 1.3, 2006-01-25
B
B
.
or by
Pin Descriptions
QuadLIU
PEF 22504
TM