pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 48

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 2
Pin No.
37
Data Sheet
Name
XL1.3
XDOP3
XOID3
I/O Signals for P-TQFP-144-8 (cont’d)
Pin Type
O
(analog)
O
O
Buffer
Type
–
–
–
Function
Transmit Line 1, port 3
Analog output to the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit FMR0.XC1 is set and XPM2.XLT is
cleared.
Transmit Data Output Positive, port 3
This digital output for transmitted dual-rail PCM(+) route
signals can provide
•
•
The data is clocked with positive transitions of XCLK3 in both
cases. Output polarity is selected by bit LIM0.XDOS (after
reset: active low). The dual-rail mode is selected if LIM1.DRS
and FMR0.XC1 are set. After reset this pin is in high-
impedance state until register LIM1.DRS is set and
XPM2.XLT is cleared.
Transmit Optical Interface Data, port 3
Unipolar data sent to a fiber-optical interface with 2048 kbit/s
(E1) or 1544 kbit/s (T1/J1) which is clocked on the positive
transitions of XCLK. Clocking of data in NRZ code is done
with 100% duty cycle. Data in CMI code is shifted out with
50% or 100% duty cycle on both transitions of XCLK3
according to the CMI coding. Output polarity is selected by bit
LIM0.XDOS (after reset: data is sent active high). The single-
rail mode is selected if LIM1.DRS is set and FMR0.XC1 is
cleared. After reset this pin is in high-impedance state until
register LIM1.DRS is set and XPM2.XLT is cleared.
48
Half bauded signals with 50% duty cycle (LIM0.XFB = 0
or
Full bauded signals with 100% duty cycle (LIM0.XFB =
1
B
)
Rev. 1.3, 2006-01-25
Pin Descriptions
QuadLIU
PEF 22504
TM
B
)