pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 76

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Masked Interrupts Visible in Status Registers
•
•
PLL Interrupt Status Register
•
•
•
The additional interrupt mode is useful when some interrupt status bits are to be polled in the individual interrupt
status registers.
Table 10
GCR.VIS; IPC.VISPLL
0
0
1
1
Note:
1. In the visible mode, all active interrupt status bits, whether the corresponding actual interrupt is masked or not,
2. All unmasked interrupt statuses are treated as before.
Please note that whenever polling is used, all interrupt status registers concerned have to be polled individually
(no “hierarchical” polling possible), since GIS only contains information on actually generated, i.e. unmasked
interrupts.
3.5.4
In the QuadLIU
state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller
and boundary scan, meet the requirements given by the JTAG standard IEEE 1149.1-2001.
overview,
parameters.
Data Sheet
The “Global” Interrupt Status register (GIS) indicates those interrupt status registers with active interrupt
indications (bits GIS.ISR(7:0)).
An additional interrupt mode can be selected per port via bit GCR.VIS (GCR). In this mode, masked interrupt
status bits neither generate an interrupt on pin INT nor are they visible in GIS, but are displayed in the
corresponding interrupt status registers ISR(1:4), ISR6 and ISR7.
The bit n (n = 1 to 4) of the register CIS pointers an interrupt on channel n.
The Global Interrupt Status register GIS2 indicates the lock status of the (global) PLL. Masking can be done
by the register GIMR.
An additional interrupt mode can be selected per port via bit IPC.VISPLL (IPC) where the masked interrupt
status bit GIS2.PLLLS does not generate an interrupt on pin INT, but is displayed in the corresponding
interrupt status register bit GIS2.PLLLC.
are reset when the interrupt status register is read. Thus, when polling of some interrupt status bits is desired,
care must be taken that unmasked interrupts are not lost in the process.
Figure 49
Interrupt Modes
Boundary Scan Interface
TM
a Test Access Port (TAP) controller is implemented. The essential part of the TAP is a finite
shows the timing diagram and
Appropriate Mask bit
0
1
0
1
76
Interrupt active
Yes
No
Yes
No
Table 58
gives the appropriate values of the timing
Visibility in ISR(1:4),
ISR(6:7) and GIS2
Yes
No
Yes
Yes
Functional Description
Rev. 1.3, 2006-01-25
Figure 19
QuadLIU
PEF 22504
gives an
TM