pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 74

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Figure 16
is marked by the falling edge of the chip select signal CS whereas the end of the operations is marked by the rising
edge of CS. Because of CS the SPI interface has no slave address.
The first bit of the serial data in (SDI) is ´1´ for a read operation and ´0´ for a write operation. The first four bits of
the 15 bit address are not valid for the QuadLIU
In read operation the QuadLIU
(SDO).
In general SPI data are driven with the negative edge of the serial clock (SCLK) and sampled with the positive
edge of SCLK.
values.
Figure 16
Figure 17
3.5.3
Special events in the QuadLIU
micro controller to read status information from the QuadLIU
electrical characteristics (open drain or push-pull) is programmed defined by the register bits IPC.IC(1:0), see IPC.
The QuadLIU
defined by registers IPC) too.
Since only one INT request output is provided, the cause of an interrupt must be determined by the external micro
controller by reading the QuadLIU
pin INT and the interrupt status bits are reset by reading the interrupt status registers. The interrupt status registers
ISR are of type “clear on read“ (“rsc”).
The structure of the interrupt status registers is shown in
Data Sheet
and
SPI Read Operation
SPI Write Operation
Interrupt Interface
TM
Figure 17
Figure 58
SCLK
SCLK
has a single interrupt output pin INT with programmable characteristics (open drain or push-pull,
SDO
SDO
SDI
CS
SDI
CS
show the read and the write operation respectively. The start of a read or write operation
shows the timing of the SPI interface and
x
x
x
x
TM
TM
x
x
high impedance
high impedance
are indicated by means of an interrupt output INT, which requests the external
delivers the 8 bit wide content of the addressed register at the serial data out
TM
x
x
’s interrupt status registers (GIS, ISR(1:4), ISR6 and ISR7). The interrupt on
x
x
A9
A9
10 bit address
10 bit address
TM
.
74
Figure
TM
, or to transfer data from/to the QuadLIU
A0
A0 D7
18.
D7
Table 63
don´t care
8 bit data
8 bit data
the appropriate timing parameter
D0
D0
Functional Description
Q LIU _SPI_w rite
Q LIU _SPI_read
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
TM
. The
TM