tea1781 NXP Semiconductors, tea1781 Datasheet - Page 14

• Manufacturer Part Number: tea1781
• Description: Greenchip Pc Secondary Control Ics
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TEA1781_82_1
Preliminary data sheet
7.10 Pull-down main outputs
7.11 OPTO control
7.9 PowerOK
The PowerOK signal is active HIGH when the main output voltages (12 V, 5 V and 3.3 V)
are within their regulation limits.
The PGOOD output is pulled down by the TEA1781T when either the 5 V or 3.3 V is below
its lower limit, or by the TEA1782T when the 12 V is below its lower limit. When all main
outputs are above their minimum value, the PGOOD signal slowly rises from zero to the
VDD level. Once the PGOOD signal exceeds V
high.
A delay can be set between the output voltages reaching their end value and the PWROK
signal being active high via an RC network connected to the PGOOD pins.
According to the Intel ATX specification, the main outputs (3.3 V, 5 V and 12 V) must be at
ground level in Standby mode. Therefore, these outputs are pulled low when the system is
in Standby mode.
The pull-down transistors for the 3.3 V and 5 V outputs are integrated in the TEA1781T,
whereas the pull-down transistor for the 12 V is integrated in the TEA1782T.
The TEA1782T defines the mode of operation of the system. It communicates with the
TEA1781T via the ENABLE pin and with the TEA1771T primary controller via the opto
coupler connected to the OPTO control block. Depending on the mode of operation, the
current to the opto coupler has the following values:
Fig 12. PowerOK circuit diagram
PWROK
VOUT_5V
5 V standby
Protection 5 V
V
PWROK
uvp
PowerOK
Rev. 01 — 13 February 2009
V
PGOOD
VOUT_3V3
Protection 3.3 V
Figure 12
V
uvp
PGOOD
PowerGood
shows the corresponding block diagram.
TEA1781T; TEA1782T
TEA1781
PGOOD
GreenChip PC secondary control ICs
VDD
, the PWROK signal becomes active
PGOOD
PowerGood
Protection 12 V
© NXP B.V. 2009. All rights reserved.
V
TEA1782
uvp
VOUT_12V
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