tda4855 NXP Semiconductors, tda4855 Datasheet - Page 22

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tda4855

Manufacturer Part Number
tda4855
Description
Autosync Deflection Controller Asdc
Manufacturer
NXP Semiconductors
Datasheet

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15. The superimposed logarithmic parabola at EWTRP (pin 20) tracks with internal VGA settings and with VPOS, but
16. If f
17. First pole of transconductance amplifier is 5 MHz without external capacitor (will become the second pole, if the OTA
18. Open-loop gain is
Vertical and EW adjustments
1996 Jul 18
handbook, halfpage
Autosync Deflection Controller (ASDC)
(1)
not with VAMP settings (see Fig.17).
be changed proportional to I
operates as an integrator).
VAMP
I VOUT2
I VOUT1
H
Fig.3 I
VGA presets disabled, VPOS centred and VSCOR = 0%.
I
tracking is enabled, the amplitude of the complete EWDRV output signal (parabola + DC shift + trapezium) will
1
is the maximum amplitude setting at VAMP (pin 18);
=
------- -
VOUT1
I
I
2
1
100%
and I
V
------------- -
V
BOP
BIN
VOUT2
at f = 0 with no resistive load and C
as functions of time.
HREF
. The EWDRV low level of 1.2 V remains fixed.
l 2
MBG590
t
l 1
(1)
22
handbook, halfpage
BOP
EWPAR = 0 to V
V EWDRV
= 4.7 nF (from BOP (pin 3) to GND).
Fig.4 V
PAR(EWDRV)
EWDRV
.
as a function of time.
Preliminary specification
TDA4855
V PAR(EWDRV)
MBG591
t

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