pnx8526 NXP Semiconductors, pnx8526 Datasheet
pnx8526
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pnx8526 Summary of contents
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... Rev. 02 — 11 July 2005 1. General description The PNX8526 is a highly integrated media processor for use in Advanced Set Top Boxes (ASTB) and Digital Television (DTV) systems. The PNX8526 is targeted at the mid to high-end ASTB/DTV systems, decoding ‘all format’ HD and SD MPEG-2 source material with Standard Defi ...
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... Applications Advanced Set Top Box (ASTB) Digital Television (DTV) 4. Ordering information Table 1: Type number PNX8526EH/M0 PNX8526EH/M0/G HBGA456 [1] Lead-free (Pb-free) package. 9397 750 15101 Product data sheet Programmable source decoder with integrated peripherials 2 C-bus, UART, USB, etc.) on the chip, other peripherals supported ...
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... TM-DBG TM32 MEDIA PROCESSOR 5 issue, 200 MHz 32 kB I-cache 16 kB 2-port D-cache 128 32-bit registers PCI (includes NAND/nor flash, IDE drive and 68 kB peripheral capability) Rev. 02 — 11 July 2005 PNX8526 PNX8526 TS_OUT DV_OUT1 AICP1 656/HD/VGA OUTPUT MODE DV_OUT2 AICP2 656 ...
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... AE3 I/O multiplexed address or data bit 23 AF4 I/O multiplexed address or data bit 22 Rev. 02 — 11 July 2005 PNX8526 PNX8526EH 001aac986 for maximum ratings). for more details. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Alternate function ...
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... Y4 I/O auxiliary arbitration PCI_GNT_A is asserted to indicate bus access has been granted to an external PCI master; used where internal arbiter is configured Rev. 02 — 11 July 2005 PNX8526 …continued for more details. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Alternate function # ...
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... AD[31:0 asserted during writes to indicate the target is prepared to accept data; wait states are inserted until PCI_IRDY and PCI_TRDY are both asserted Rev. 02 — 11 July 2005 PNX8526 …continued for more details. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Alternate ...
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... J23 I/O memory data bit 50 H26 I/O memory data bit 49 H25 I/O memory data bit 48 H23 I/O memory data bit 47 Rev. 02 — 11 July 2005 PNX8526 for more details. for more details. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Alternate function # # # # # # Alternate function ...
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... B13 I/O memory data bit 12 C13 I/O memory data bit 11 D13 I/O memory data bit 10 A12 I/O memory data bit 9 B12 I/O memory data bit 8 Rev. 02 — 11 July 2005 PNX8526 for more details. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Alternate function ...
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... AD14 I/O general purpose input/output bit 5 AC14 I/O general purpose input/output bit 4 C5 I/O general purpose input/output bit 3 Rev. 02 — 11 July 2005 PNX8526 for more details. for more details. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Alternate function Alternate function # # # ...
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... C6 I/O data minus bit 0 D7 I/O data minus bit USB port power on/off 0 = power power off Rev. 02 — 11 July 2005 PNX8526 …continued for more details. for more details. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Alternate function # # # Alternate function # ...
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... AICP M1 O digital video output1; bit 8 for primary display channel from AICP N4 O digital video output1; bit 7 for primary display channel from AICP Rev. 02 — 11 July 2005 PNX8526 2 C-bus) clock 2 C-bus) data 2 C-bus) clock 2 C-bus) data for more details. ...
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... M4 O blanking for primary display AD20 O audio IN1oversample clock AC19 I/O audio IN1 serial clock AF21 I/O audio IN1 word select Rev. 02 — 11 July 2005 PNX8526 for more details. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Alternate function ...
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... ITU-656 VIP data bit 0 (least significant bit) AF20 I/O ITU-656 VIP data valid AE20 I/O ITU-656 VIP data clock AF23 I digital video transport stream2 data bit 7 Rev. 02 — 11 July 2005 PNX8526 for more details. for more details. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Alternate function # # # # # ...
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... AA24 I/O transport stream start of packet (parallel/serial) AA25 I/O transport stream data valid (parallel/serial) AA26 I/O transport stream clock (parallel/serial) Rev. 02 — 11 July 2005 PNX8526 for more details. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Alternate function # # # # # # ...
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... V P22 system 1.26 V N22 system 1.26 V K22 system 1.26 V J22 system 1. system 1. system 1. system 1. system 1. system 1. system 1. system 1. system 1. system 1.26 V Rev. 02 — 11 July 2005 PNX8526 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... V Y5 system 3 system 3.3 V (CAB) H5 system 3.3 V (CAB) AB15 system 3.3 V (TM-PLL) AF25 system ground AF26 system ground AE26 system ground AE25 system ground AC23 system ground Rev. 02 — 11 July 2005 PNX8526 …continued © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... AC4 system ground AD3 system ground AE2 system ground AE1 system ground AF1 system ground AF2 system ground F5 system ground E5 system ground E6 system ground D4 system ground Rev. 02 — 11 July 2005 PNX8526 …continued © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... All pins (in alpha-numeric sequence) Pin Group Type A1 PWR - A2 PWR - A3 TEST C-bus I/O Rev. 02 — 11 July 2005 PNX8526 …continued Description system ground system ground PR3940 debug port data in 2 serial communications port (I C-bus) data © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... I/O B7 1394 I/O B8 1394 I/O B9 1394 I/O Rev. 02 — 11 July 2005 PNX8526 …continued Description data plus bit 1 signals type of isolation mode used at the PHY-Link interface 0 = 1394-1995 annex J type isolation; enables differentiator circuitry 1 = direct connection or single capacitor isolation mode; this will disable the differentiator circuitry PHY data bit 0; data is expected on ports 1:0 for 100 MB packets PHY data bit 4 ...
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... MMI O C20 MMI O C21 MMI O C22 MMI O Rev. 02 — 11 July 2005 PNX8526 …continued Description memory data bit 1 memory data bit 5 memory data bit 8 memory data bit 12 SDRAM control bit 2 memory data bit 19 memory data bit 23 memory data bit 27 memory data bit 30 ...
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... E6 PWR - E7 PWR - E8 PWR - Rev. 02 — 11 July 2005 PNX8526 …continued Description memory clock enable system ground memory data bit 32 memory clock bit 1 system 1.26 V system ground (analog ground 1.728 GHz PLL) PLL reference crystal feedback driver system ground general purpose input/output bit 1 ...
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... MMI I/O G25 MMI I/O G26 MMI I C-bus I/O H2 TEST O H3 TEST I Rev. 02 — 11 July 2005 PNX8526 …continued Description system 1.26 V system 1.26 V system 3.3 V system 3.3 V system 1.26 V system 1.26 V system 1.26 V system 3.3 V system 3.3 V system 1.26 V system 1.26 V system 3.3 V system 3.3 V system ground memory data bit 34 memory data bit 37 memory data bit 38 SDRAM control bit 5 system 1 ...
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... PWR - L22 PWR - L23 MMI I/O L24 MMI I/O Rev. 02 — 11 July 2005 PNX8526 …continued Description system 1.26 V system 3.3 V (CAB) system 3.3 V memory data bit 47 SDRAM control bit 6 memory data bit 48 memory data bit 49 audio OUT1 serial clock audio OUT1 data audio OUT1 word select JTAG data IN system 1 ...
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... COM O N26 GPIO I/O P1 AVIF O Rev. 02 — 11 July 2005 PNX8526 …continued Description memory data bit 59 memory data bit 60 digital video output1; bit 8 for primary display channel from AICP digital video output1; bit 9 for primary display channel from AICP digital video clock1 for primary display channel ...
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... O T1 AVIF O T2 AVIF O Rev. 02 — 11 July 2005 PNX8526 …continued Description digital video output1; bit 3 for primary display channel from AICP digital video output1; bit 0 for primary display channel from AICP digital video output1; bit 1 for primary display channel from AICP system 1 ...
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... I V24 DVB I V25 DVB I V26 DVB I Rev. 02 — 11 July 2005 PNX8526 …continued Description digital video output2; bit 4 for secondary display channel from AICP digital video output2; bit 2 for secondary display channel from AICP system 3.3 V system ground system ground system ground system ground ...
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... I AA2 PCI I/O AA3 PCI I/O AA4 PCI I/O Rev. 02 — 11 July 2005 PNX8526 …continued Description USB port power on/off 0 = power power off indicates over current being drawn by a USB device 0 = over current detected over current PCI bus global reset general purpose PLL clock output system 3 ...
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... AC7 PCI I/O AC8 PCI I/O AC9 PCI I/O Rev. 02 — 11 July 2005 PNX8526 …continued Description system ground system ground transport stream data bit 4 transport stream start of packet (parallel/serial) transport stream data valid (parallel/serial) transport stream clock (parallel/serial) multiplexed address or data bit 31 multiplexed address or data bit 30 ...
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... AD20 AVIF O AD21 AVIF O AD22 DVB I Rev. 02 — 11 July 2005 PNX8526 …continued Description multiplexed address or data bit 7 multiplexed address or data bit 3 multiplexed address or data bit 0 external input/output select1 general purpose input/output bit 4 audio input/output word select multi-channel/SPDIF Output ITU-656 VIP data bit 6 ...
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... PCI I/O AF4 PCI I/O AF5 PCI I/O Rev. 02 — 11 July 2005 PNX8526 …continued Description digital video transport stream2 data bit 2 digital video transport stream2 start of packet digital video transport stream2 data valid digital video transport stream2 error system ground system ground multiplexed address or data bit 23 ...
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... Multi-function pins Table 16 Section 6.2 of signals. Remark: The PNX8526 has a number of General Purpose Input Output (GPIO) pins. Some of these are dedicated pins, while others are configured as alternate signals on multifunction pins. The standard function of these pins may not be required in some system configurations. ...
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... SPY micro-architecture output signal, bit 4 O program counter status1, bit 0 O digital video output2, bit 3 for secondary display channel from AICP O SPY micro-architecture output signal, bit 3 O program counter status0, bit 2 Rev. 02 — 11 July 2005 PNX8526 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... I ITU-656 VIP data bit 4 I/O general purpose input/output 37 I ITU-656 VIP data bit 3 I/O general purpose input/output 36 I ITU-656 VIP data bit 2 I/O general purpose input/output 35 Rev. 02 — 11 July 2005 PNX8526 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... ITU-656 VIP data bit 0 (least significant bit) I digital video transport stream2 serial error1 I digital video transport stream2 data valid I ITU-656 VIP data valid I digital video transport stream2 serial valid1 Rev. 02 — 11 July 2005 PNX8526 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... I digital video transport stream3 clock I ITU-656 VIP data clock I digital video transport stream3 serial clock1 O transport stream data bit 7 I/O general purpose input/output 29 Rev. 02 — 11 July 2005 PNX8526 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... I/O general purpose input/output 60 [2] O external MMIO select 2 I/O general purpose input/output 54 [2] O external MMIO select 1 I/O general purpose input/output 53 [2] O external MMIO select 0 I/O general purpose input/output 52 Rev. 02 — 11 July 2005 PNX8526 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... ICAM2 VPP I/O general purpose input/output 9 I select configuration bit 2 during system reset I/O general purpose input/output 2 I select configuration bit 1 during system reset I/O general purpose input/output 1 Rev. 02 — 11 July 2005 PNX8526 [3] [3] © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... In this table ‘type’ reflects MUX pin function only. A pin may have other ‘type’ capabilities as noted in its functional group. [2] These pins are included in the XIO set. Refer to “PNX8526 User Manual, Chapter 8" for additional functions. [3] The ICAM1_SETVPP and ICAM1_C8 signals are automatically selected when the ICAM function is selected ...
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... Based on the system implementation, one or both transport streams may pass through Point Of Deployment (POD) or Common Interface (CI) conditional access modules before transfer into the PNX8526. Either a single companion IC, such as the SCM microsystems CIMaX, or two CIMaX chips can be used. In the latter case possible to handle dual decoding no matter which conditional access system is used ...
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... TM32 CPU and/or the memory based scaler prior to invoking the compositing/display engine. This is subject to CPU and memory bandwidth availability. The PNX8526 contains a 1394 interface with 5C copy protection. The PNX8526 1394 can simultaneously transmit two transport streams while receiving one transport stream. The transmitted streams can be partial transport streams (created by PID fi ...
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... SPDIF in IR remote USB (2 ) UART2 IrDA data (UART1) smart card (2 ) PCI-XIO8 expansion bus DOCSIS MODEM Fig 3. PNX8526-based system block diagram 8. I/O multiplexer control register The I/O multiplexer control register is used to configure the multifunction pins to alternate functions as described in IO_MUX_CTRL Table 17: Global 2 registers Bit Symbol ...
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... VIP data from DV3 port 010 VIP data from DV_OUT2 (AICP2) port 011 1394 data from link core 100 (1.26 V) DDC (1. stabilize (approximately 100 ms recommended) DDC (3.3 V). DD Rev. 02 — 11 July 2005 PNX8526 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... V esd 11. Thermal characteristics PNX8526 can be used in different environments creating different junction temperatures. The thermal resistance from junction to ambient (R package is approximately 11.7 K/W. This value is achieved using natural convection, no external heatsink and using a JEDEC-defined printed-circuit board with high thermal conduction (see “JEDEC standards 51-2 and 51-7” for details). ...
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... Philips Semiconductors Given the power dissipation of the PNX8526 and the ambient temperature inside the enclosure, the expected junction temperature can be calculated using the following equation amb In some applications the junction temperature may be judged too high, reducing the acceptable lifetime (see additional external heatsink, or increasing the airfl ...
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... mA): OH3 (14 mA mA): OH4 Rev. 02 — 11 July 2005 …continued [1] Min Typ 2 0.9 - 0.13 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. PNX8526 Max Unit - 3.5 pF 1 ...
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... Philips Semiconductors 12.1 Reset timing Fig 5. Reset timing Table 21: Symbol t LOW 12.2 Peripheral Controller Interface (PCI) timing For additional timing diagram information on XIO and IDE interfaces see “PNX8526 User Manual, Chapter 8" . Fig 6. PCI timing Table 22: Symbol Parameter 9397 750 15101 ...
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... MMI control and address MMI DATA MMI timing (with reference to MCLK) Parameter CS setup time CS hold time data output setup time data output hold time data input setup time data input hold time Rev. 02 — 11 July 2005 PNX8526 Conditions Min Typ [ ...
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... Parameter Conditions pulse width GPIO as input GPIO as output UART TX/RX 1.5 V RTSN/CTSN UART output timing (with reference to UART clock) Parameter Conditions pulse width UART TX UART RX UART RTSN UART CTSN Rev. 02 — 11 July 2005 PNX8526 …continued Conditions Min Typ 2 MIN 001aad371 Min Typ Max [1] ...
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... SSI timing (with reference to MCLK) Parameter CS setup time CS hold time data output setup time data output hold time data input setup time data input hold time clock LOW time clock HIGH time Rev. 02 — 11 July 2005 PNX8526 t clk(L) clk( valid t t ...
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... SCL LOW time SCL HIGH time data setup time data hold time SCL LOW to data out valid SCL HIGH to data out t su Rev. 02 — 11 July 2005 PNX8526 t LOW t h(STA h(SDA) dv(STO) t su(SDA) ...
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... I S-bus audio input and output timing Fig 13. I Table 30: Timing is with respect to the SCK clock edge. The PNX8526 is the source of AI_WS. Symbol Parameter f AI_SCK t su(CLK) t h(CLK) t ws(SCK) 9397 750 15101 Product data sheet Programmable source decoder with integrated peripherials ...
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... AO_SCK frequency audio-out clock AO_SCK to audio-out data AO_SD valid audio-out clock AO_SCK to audio-out word-select AO_WS valid t HIGH SPDIF timing Conditions clock HIGH time (PCI) clock LOW time (PCI) Rev. 02 — 11 July 2005 PNX8526 t dv(SCK) valid t ws(SCK) valid mce552 Conditions Min Typ - ...
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... HSYNC, VSYNC, BLANK hold time CLOCK INPUTS (DATA, SOP, ERROR, VALID) DV input timing (referenced to input video clock) Conditions DVB clock frequency input data setup time input data hold time Rev. 02 — 11 July 2005 PNX8526 t t su(CLK) h(CLK) valid t dv(CLK) valid mce554 Min Typ ...
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... Product data sheet Programmable source decoder with integrated peripherials CLOCK OUTPUT (DATA, SOP, VALID) TSO timing data setup time data hold time Rev. 02 — 11 July 2005 PNX8526 mce556 Conditions Min Typ © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... Philips Semiconductors 13. Application information 13.1 Differences between PNX8525 and PNX8526 There are a number of differences between the PNX8525 and the PNX8526 with respect to the physical interfacing of the device. These differences are described in Table 36: PNX8525 Core supply voltage 1 C-bus pads GPIO pads with Schmitt trigger and pull-ups ...
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... Useful life (years function of junction temperature ( C cumulative failures; 8 hours/day. Figure 19 junction temperature of 110 year lifetime can be Section Rev. 02 — 11 July 2005 PNX8526 mgx461 110 115 120 125 11. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... 35.2 30.75 35.2 30.75 1.27 31.75 34.8 29.75 34.8 29.75 REFERENCES JEDEC JEITA MS-034 - - - Rev. 02 — 11 July 2005 detail 0.2 0.35 31.75 0.3 0.15 22 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. PNX8526 SOT610-1 ISSUE DATE 00-12-13 02-01- ...
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... C (SnPb process) or below 245 C (Pb-free process) – for all BGA, HTSSON..T and SSOP..T packages 9397 750 15101 Product data sheet Programmable source decoder with integrated peripherials Rev. 02 — 11 July 2005 PNX8526 ). If the stg(max) © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C. 9397 750 15101 Product data sheet Programmable source decoder with integrated peripherials 2 called small/thin packages. Rev. 02 — 11 July 2005 PNX8526 3 350 mm so called © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... LBGA, not suitable [5] , not suitable , SO, SOJ suitable not recommended not recommended [10] [10] , WQCCN..L not suitable Rev. 02 — 11 July 2005 PNX8526 [2] Reflow [3] not suitable suitable [6] suitable suitable [7] [8] suitable [9] suitable not suitable © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Dipping ...
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... Security standard for Japanese market National TV Systems Committee Operating System Phase Alternate Line Peripheral Component Interconnect Pulse Code Modulation Program Identifier Phase-Locked Loop Red Green Blue Read Only Memory Rev. 02 — 11 July 2005 PNX8526 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Systeme Electronique Couleur Avec Memoire Sony Philips Digital Interface Synchronous Serial Interface Transport Stream Output Universal Asynchronous Receiver Transmitter Universal Serial Bus Very Long Instruction Word Extended Input Output Rev. 02 — 11 July 2005 PNX8526 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Programmable source decoder with integrated peripherials Data sheet status Change notice Product data sheet - Preliminary data sheet - Rev. 02 — 11 July 2005 PNX8526 Doc. number Supersedes 9397 750 15101 PNX8526_1 9397 750 11715 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... I C-bus — wordmark and logo are trademarks of Koninklijke Philips Electronics N.V. TriMedia — trademark of Koninklijke Philips Electronics N.V. Nexperia — trademark of Koninklijke Philips Electronics N.V. Rev. 02 — 11 July 2005 PNX8526 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... S-bus audio input and output timing 12.10 SPDIF timing 12.11 Digital video output (DV_OUT) timing 12.12 Digital video input (DV Input) timing . . . . . . . . 53 12.13 Transport Stream Output (TSO) timing . . . . . . 54 13 Application information 13.1 Differences between PNX8525 and PNX8526 55 13.2 Lifetime versus temperature . . . . . . . . . . . . . . 56 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 57 15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15.2 Through-hole mount packages . . . . . . . . . . . . 58 15.2.1 Soldering by dipping or by solder wave ...