is42g32256 ETC-unknow, is42g32256 Datasheet

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... Write per bit (old mask) • Block write (eight columns) DESCRIPTION The ISSI IS42G32256 is a high-speed 16-Mbit CMOS Synchronous Graphics RAM organized as 256K words x 32 bits x 2 banks. With SGRAM, all input and output signals are synchronized with the rising edge of the system clock ...

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... IS42G32256 BLOCK WRITE CONTROL LOGIC COLUMN MASK CLK CKE CS RAS CAS WE DSF DQM0-3 Figure 1. IS42G32256 Functional Block Diagram 2 DQM0-3 WRITE MUX CONTROL LOGIC 256K x 32 MEMORY CELL ARRAY ROW DECODER REFRESH COUNTER ADDRESS BUFFER INPUT REGISTER CLOCK MASK REGISTER COLOR REGISTER ...

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... DQ20 DQ21 GND Q DQ22 DQ23 V CCQ DQM0 DQM2 WE CAS RAS CS BA (A10) A8 Figure 2. IS42G32256 Pin Configuration, 100-pin PQFP Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR037-0C 09/10/98 100 ...

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... IS42G32256 Table 2. Pin Descriptions Symbol Pin Number A0-A9 30-34, 47-51 A10/BP 29 CAS 26 CKE 54 CLK DQ0-DQ31 1, 3-4, 6-7, 9-10, 12-13, 17-18, 20-21, 60-61, 63-64, 68-69, 71-72, 74-75, 77-78, 81-81, 83-84, 97-98, 100 DQM0-DQM3 23-24, 56-57 DSF 53 RAS 14, 22, 59, 67, 73, 76, 79 CCQ Vcc 15, 35, 65, 96 GND 5, 11, 19, 62, 70, 82 GND 16, 46, 66 36-45, 52, 58, 86-95 4 I/O Name and Function I Address: Row/Column addresses are multi- plexed on the same pins ...

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... MHz (8 ns 100 MHz (10 ns MHz (12 ns MHz (13.4 ns MHz (15 ns MHz (20 ns IS42G32256 (Unit: number of clocks) CAS CAS CAS CAS CAS t RC Frequency Latency 80 ns 100 MHz (10 ns MHz (12 ns MHz (14 ns) ...

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... IS42G32256 Table 4. Truth Table Function CKEn-1 (2,3) Mode Register Set (2,3,8) Special Mode Register Set Auto Refresh (4) Self Refresh, Entry (4) Self Refresh, Exit (4) Bank Active/Row Address Write Per Bit Disable (5,6) Bank Active/Row Address Write Per Bit Enable (5,6,10) Read and Column Address Auto Precharge Disable ...

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... IS42G32256 Table 5. SGRAM vs SDRAM SDRAM Function DSF L SGRAM Function MRS SMRS Notes DSF is low, SGRAM functionality is identical to SDRAM functionality. 2. SGRAM can be used as a unified memory by the appropriate DSF control; SGRAM = Graphic Memory + Main Memory. Table 6. Mode Register Field Table to Program Modes ...

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... IS42G32256 Table 7. Burst Sequence (Burst Length = 4) Initial Address Table 8. Burst Sequence (Burst Length = 8) Initial Address Table 10 ...

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... IS42G32256 DEVICE OPERATIONS Clock (CLK) The clock input is used as the reference for all SGRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V and V . During operation with IL IH CKE high all inputs are assumed valid state (low ...

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... IS42G32256 CAS uses A3, latency (read latency from column address) A4-A6, A7-A8 and A10 are uses for vendor specific options or test mode use. And the write burst length is programmed using A9. A7-A8 and A10 must be set to low for normal SGRAM operation. Refer to the table for specific codes for ...

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... IS42G32256 The minimum number of clock cycles required to complete row precharge is calculated by dividing “t cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by t (max) ...

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... IS42G32256 issued. SMRS, compared with MRS, can be issued at the active state under the condition that DQs are idle write operation, SMRS accepts the data needed through DQ pins. Therefore it should be attended not to induce bus contention. The more detailed materials can be obtained by referring corresponding timing diagram ...

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... IS42G32256 Table 11. Summary of SGRAM Basic Features and Benefits Features 256K SGRAM Interface Synchronous Bank 2 each Page Depth /1 Row 256 bit Total Page Depth 2048 bytes Burst Length (Read Full Page Burst Length (Write Full Page ...

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... IS42G32256 BASIC FEATURES AND FUNCTION DESCRIPTION 1. CLOCK SUSPENDED DURING WRITE (BURST LENGTH = 4) CLK COMMAND WR CKE MASKED BY CKE INTERNAL CLK DQ (CLOCK D0 D1 LATENCY = 2) DQ (CLOCK D0 D1 LATENCY = 3) Note: 1. CKE to CLK disable/enable = 1 clock. 1. WRITE MASK (BURST LENGTH = 4) CLK COMMAND WR DQM MASKED BY CKE DQ (CLOCK ...

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... IS42G32256 1. READ INTERRUPTED BY READ (BURST LENGTH = 4) (SEE NOTE 1.) CLK COMMAND RD RD ADD (CLOCK QA0 LATENCY = 2) DQ (CLOCK LATENCY = 3) t CCD (SEE NOTE 2) 2. WRITE INTERRUPTED BY (BLOCK) WRITE (BURST LENGTH = 2) CLK COMMAND CCD (NOTE 2) ADD DA0 DB0 DB1 t CDL (NOTE 3) 4 ...

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... IS42G32256 1. CLOCK LATENCY = 2, BURST LENGTH = 4. CLK CMD 1 RD DQM DQ CMD 2 RD DQM DQ CMD 3 RD DQM DQ CMD 4 RD DQM DQ 2. CLOCK LATENCY = 3, BURST LENGTH = 4. CLK CMD 1 RD DQM DQ CMD 2 RD DQM DQ CMD 3 RD DQM DQ CMD 4 RD DQM DQ CMD 5 RD DQM DQ Notes prevent bus contention, there should be at least one gap between data in and data out. ...

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... IS42G32256 CLK COMMAND DQM DQ Notes Inhibit invalid write, DQM should be issued. 2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual banks operation. Figure 8. Write Interrupted by Precharge and DQM 1 ...

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... IS42G32256 1. NORMAL WRITE (BURST LENGTH = 4) CLK COMMAND READ (BURST LENGTH = 4) CLK COMMAND RD DQ (CLOCK LATENCY = 2) DQ (CLOCK LATENCY = 3) Note: 1. The row active command of the precharge bank can be issued after t The new read/write command of other activated bank can be issued from this point. ...

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... IS42G32256 1. MODE REGISTER SET CLK (NOTE 4) COMMAND PRE t RP Notes CLK; last data in to Row Precharge. RDL CLK; last data in to Burst Stop Delay. BDL 3. Number of valid output data after Row Precharge or Burst Stop for 4. PRE: Both banks precharge, if necessary. ...

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... IS42G32256 1. AUTO REFRESH (NOTE 3) CLK (NOTE 4) CMD PRE CKE SELF REFRESH (NOTE 6) CLK (NOTE 4) CMD PRE CKE t RP Notes: 1. Active power down: one or more banks active state. 2. Precharge power down: both banks precharge state. 3. The Auto Refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after Auto Refresh command ...

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... IS42G32256 Table 11. About Burst Type Control Basic Mode Sequential Counting Interleave Counting Pseudo-Mode Pseudo-Document Sequential Counting Pseudo-Binary Counting Random Mode Random Column Access, t CCD Table 12. About Burst Length Control Basic Mode Full Page Special Mode BRSW Block Write Random Mode ...

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... IS42G32256 Table 13. Mask Function Procedure 1. Normal Write I/O masking: By Mask at Write Per Bit Mode, the selected bit planes keep the original data. If bit plane 19, 22, 24, and 31 keep the original value. a. STEP I. SMRS(LMR): Load mask [31-0]=“0111, 1110, 1011, 0111, 1111, 1101, 0111, 0110” ...

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... IS42G32256 Table 13. Mask Function Procedure (continued) b. Illustration I/O (=DQ) (1) 31 DQMi DQM3=0 Color Register Color3=Blue Before Block Write & DQ (Pixel data) 000 White DQ24=H 001 White DQ25=H 010 White DQ26=H 011 White DQ27=L 100 White DQ28=H 101 White DQ29=H 110 White DQ30=H 111 ...

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... IS42G32256 Table 13. Mask Function Procedure (continued) b. Illustration (1) I/O (=DQ) 31 Color Register 11000011 DQMi DQM3=0 Mask Register 11111111 Before Write Yellow 00001111 After Write 11000011 I/O (=DQ) (1) 31 DQMi DQM3=0 Color Register Color3=Blue Before Block Write & DQ (Pixel data) 000 Yellow DQ24=H 001 Yellow DQ25=H ...

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... IS42G32256 Table 14. Function Truth Table Current RAS RAS RAS RAS CAS CAS CAS WE CAS RAS CAS WE State DSF IDLE ...

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... IS42G32256 Table 14. Function Truth Table (continued) Current RAS RAS RAS RAS CAS CAS WE CAS CAS RAS CAS WE State DSF Write ...

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... IS42G32256 Table 14. Function Truth Table (continued) Current RAS RAS RAS CAS RAS CAS CAS CAS RAS CAS WE State DSF Row Activating ...

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... IS42G32256 Table 15. Function Truth Table for CKE Current CKE CKE RAS RAS RAS RAS RAS CAS State (n-1) n Self Refresh Both Bank Precharge Power Down ...

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... IS42G32256 Table 16. Absolute Maximun Ratings Symbol Parameters V Maximum Supply Voltage CC MAX V Maximum Supply Voltage for Output Buffer CCQ MAX V Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS T Operating Temperature OPR T Storage Temperature STG Table 17. DC Recommended Operating Conditions ...

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... IS42G32256 Table 19. DC Electrical Characteristics (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter I Input Leakage Current IL I Output Leakage Current OL V Output High Voltage Level OH V Output Low Voltage Level OL (1,2) I Operating Current Precharge Standby Current (In Power-Down Mode) ...

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... IS42G32256 Table 20. AC Characteristics (1,2,3) Symbol Parameter t Clock Cycle Time CK t Access Time From CLK ( CLK HIGH Level Width CHI t CLK LOW Level Width CL t Output Data Hold Time OH t Output LOW Impedance Time LZ t Output HIGH Impedance Time HZ t Input Data Setup Time ...

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... IS42G32256 Figure 21. Operating Frequency / Latency Relationships Symbol Parameter CL t Clock Cycle Time CK — Operating Frequency CAS t Latency CAC t Active Command to Read/Write Command Delay Time RCD RAS t Latency ( RAC RCD CAC t Command Period (REF to REF/ACT to ACT Command Period (ACT to PRE) ...

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... IS42G32256 AC TIMING WAVEFORMS CLK CKE HIGH LEVEL IS NECESSARY RAS CAS A0-A8 A10/ DSF DQM HIGH LEVEL IS NECESSARY DQ HIGH-Z PRECHARGE AUTO (ALL BANKS) REREFRESH Figure 18. Power On Sequence and Auto Refresh Integrated Silicon Solution, Inc. ADVANCE INFORMATION SR037-0C 09/10/ ...

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... IS42G32256 CLK t CC CKE HIGH NOTE RCD t SH RAS CAS A0- NOTE 2 A10 BS BS NOTE NOTE 5 DSF t SS DQM t RAC DQ ROW ACTIVE READ (WRITE PER BIT ENABLE OR DISABLE) Figure 19. Single Bit Read-Write-Read Cycle (Same Page) at ...

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... IS42G32256 Notes: 1. All inputs can be “Don’t Care” when 2. Bank active and read/write are controlled by A10. A10 Active and Read/Write 0 Bank A 1 Bank B 3. Enable and disable auto precharge function are controlled read/write command. A9 A10 Operation 0 0 Disable auto precharge, leave bank A active at end of burst. ...

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... IS42G32256 CLK CKE HIGH RAS CAS A0-A8 Ra Ca0 A10 DSF DQM DQ: CLOCK LATENCY = 2 t RAC NOTE 3 DQ: CLOCK LATENCY = 3 ROW ACTIVE READ (A-BANK) (A-BANK) Notes: 1. Minimum cycle time is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Length = 1] valid output data available after Row enters precharge ...

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... IS42G32256 CLK CKE HIGH RAS CAS A0-A8 Ra Ca0 A10 DSF DQM DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3 ROW ACTIVE READ (A-BANK) (A-BANK) Notes write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention ...

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... IS42G32256 CLK CKE HIGH CS RAS CAS NOTE 4 A0-A8 RAa CAa A10 DSF t CLD DQM NOTE 1 Pixel DQ Mask ROW ACTIVE WITH MASKED WRITE-PER-BIT BLOCK ENABLE WRITE (A-BANK) (A-BANK) Notes: 1. Column Mask (DQi = L: Mask, DQi = H: Non-mask Block Write Cycle time. ...

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... IS42G32256 CLK CKE HIGH CS RAS CAS A0-A2 RAa A3,A4, RAa CAa A7,A8 A5 RAa CAa A6 CAa RAa A9 RAa A9 WE DSF DQM I/O Pixel DQ Color Mask Mask LOAD LOAD MASKED COLOR MASK BLOCK REGISTER REGISTER WRITE (A-BANK) ROW ACTIVE WITH WRITE-PER-BIT ENABLE (A-BANK) Note the next clock of special mode register set command, new command is possible. ...

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... IS42G32256 CLK CKE HIGH CS RAS CAS A0-A8 RAa CAa A10 A9 RAa WE HIGH DSF DQM DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3 ROW ACTIVE (A-BANK) READ (A-BANK) Notes can be “Don’t Care” when 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. ...

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... IS42G32256 CLK CKE HIGH CS RAS CAS A0-A8 RAa KEY CAa RBb A10 A9 RAa RBb WE DSF DQM DQ Mask DAa0 DAa1 LOAD ROW MASK ACTIVE REGISTER (B-BANK) ROW ACTIVE MASKED WITH WRITE WRITE-PER-BIT (A-BANK) ENABLE (A-BANK) Figure 25. Page Write Cycle at Different Bank at Burst Length = 4 Integrated Silicon Solution, Inc ...

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... IS42G32256 CLK CKE HIGH CS RAS CAS A0-A8 RAa CAa A10 A9 RAa WE DSF DQM DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3 ROW ACTIVE READ (A-BANK) (A-BANK) Note should be met to complete write. CDL Figure 26. Read and Write Cycle at Different Bank at Burst Length = 4 42 ...

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... IS42G32256 CLK CKE HIGH CS RAS CAS A0- A10 DSF DQM DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3 ROW ACTIVE ROW ACTIVE (A-BANK) (B-BANK) Note should be controlled to meet minimum t RDL BRSW mode and Block write). Figure 27. Read and Write Cycle with Auto Precharge at Burst Length = 4 Integrated Silicon Solution, Inc ...

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... IS42G32256 CLK CKE HIGH CS RAS CAS A0- A10 DSF DQM DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3 ROW ACTIVE ROW ACTIVE (A-BANK) (B-BANK) Note: 1. When Read (Write) command with auto precharge is issued at A-Bank after A and B Bank activation. — If Read (Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank auto precharge will start at the next cycle of B Bank read command input point. — ...

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... IS42G32256 CLK CKE HIGH CS RAS CAS A0-A8 Ra A10 DSF DQM DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3 ROW ACTIVE (A-BANK) Note: 1. Any command to A Bank is not allowed in this period. t Figure 29. Read and Write Cycle with Auto Precharge ••• at Burst Length = 4 Integrated Silicon Solution, Inc ...

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... IS42G32256 CLK CKE HIGH CS RAS CAS A0-A8 RAa CAa A10 NOTE DSF DQM DQ: CLOCK LATENCY = 2 DQ: CLOCK LATENCY = 3 ROW ACTIVE (A-BANK) Notes full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. 2. About the valid DQs after burst stop same as the case of diagram. See the label 1,2 on them. But at burst write, Burst stop and Refer to the timing diagram of “ ...

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... IS42G32256 CLK CKE HIGH CS RAS CAS A0-A8 RAa CAa A10 A9 RAa WE DSF DQM DQ: CLOCK QAa0 LATENCY = 2 DQ: CLOCK QAa0 LATENCY = 3 ROW ACTIVE WRITE (A-BANK) (A-BANK) ROW ACTIVE (B-BANK) AUTO PRECHARGE Notes: 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to “ ...

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... IS42G32256 CLK CKE HIGH CS RAS CAS A0- A10 DSF DQM DQ Qa0 ROW READ ACTIVE Note: 1. DQM needed to prevent bus contention. Figure 33. Clock Suspension and DQM Operation Cycle Qa1 Qa2 Qa3 Qb0 t SHZ CLOCK ...

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... IS42G32256 CLK NOTE NOTE 1 CKE NOTE 3 CS RAS CAS A0-A8 A10 A9 WE DSF DQM DQ PRECHARGE POWER-DOWN ENTRY Notes: 1. All banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least “1CLK + t 3. Cannot violate minimum refresh specification (32 ms). ...

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... IS42G32256 CLK NOTE 2 NOTE 1 CKE RAS NOTE 7 CAS A0-A8 A10 A9 WE DSF DQM DQ HI-Z SELF REFRESH ENTRY Notes: TO ENTER SELF REFRESH MODE CS RAS CAS and with CKE should be low at the same clock cycle. 2. After one clock cycle, all the inputs including the system clock can be “Don’t Care” except for CKE. ...

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... IS42G32256 CLK HIGH CKE CS NOTE 2 RAS NOTE 1 CAS NOTE 3 A0-A8 KEY RA WE DSF DQM DQ HI-Z MRS NEW COMMAND Both bank precharge should be completed Mode Register Set cycle and auto refresh cycle. Notes: CS raS CAS and activation and DSF of low at the same clock with address key will set internal mode register ...

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... Commercial Range Frequency Speed (ns) Cycle Time 143 MHz 125 MHz 100 MHz 52 Order Part No IS42G32256-7PQ - 8 IS42G32256-8PQ -10 IS42G32256-10PQ Integrated Silicon Solution, Inc. ISSI ® Package PQFP PQFP PQFP ISSI ® 2231 Lawson Lane Santa Clara, CA 95054 Fax: (408) 588-0806 Toll Free: 1-800-379-4774 Email: sales@issi ...