is42g32256 ETC-unknow, is42g32256 Datasheet - Page 40

• Manufacturer Part Number: is42g32256
• Description: 256k 16-mbit Synchronous Graphics
• Manufacturer: ETC-unknow

IS42G32256
40
LATENCY = 2
LATENCY = 3
DQ: CLOCK
DQ: CLOCK
Notes:
1.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
CS
A0-A8
DQM
CLK
CKE
RAS
CAS
DSF
can be “Don’t Care” when
A10
WE
CS
A9
ROW ACTIVE
HIGH
HIGH
0
(A-BANK)
RAa
RAa
1
Figure 24. Page Read Cycle at Different Bank at Burst Length = 4
2
3
(A-BANK)
READ
CAa
RAS
4
(B-BANK)
ACTIVE
ROW
RBb
RBb
,
CAS
5
QAa0 QAa1
, and
6
QAa0 QAa1
WE
7
(B-BANK)
QAa2 QAa3
READ
are high at the clock high going edge.
CBb
8
QAa2 QAa3
9
QBb0 QBb1
10
QBb0 QBb1
11
(A-BANK)
QBb2 QBb3
READ
CAc
12
QBb2 QBb3
13
(B-BANK)
READ
QAc0 QAc1
CBd
Integrated Silicon Solution, Inc.
14
QAc0 QAc1
15
(A-BANK)
ADVANCE INFORMATION SR037-0C
CAe
READ
QBd0 QBd1 QAe0 QAe1
16
QBd0 QBd1 QAe0 QAe1
PRECHARGE
17
(A-BANK)
NOTE 2
: DON’T CARE
18
ISSI
19
09/10/98
®