is42g32256 ETC-unknow, is42g32256 Datasheet - Page 6

• Manufacturer Part Number: is42g32256
• Description: 256k 16-mbit Synchronous Graphics
• Manufacturer: ETC-unknow

IS42G32256
6
Table 4. Truth Table
Function
Mode Register Set
Special Mode Register Set
Auto Refresh
Self Refresh, Entry
Self Refresh, Exit
Bank Active/Row Address
Bank Active/Row Address
Read and Column Address
Read and Column Address
Write and Column Address
Write and Column Address
Block Write and Column Address
Block Write and Column Address
Burst Stop
Precharge Bank Selection
Precharge Both Banks
Clock Suspend or
Clock Suspend or
Precharge Pover Down Mode Entry
Precharge Pover Down Mode Exit
DQM
No Operation Command
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Graphic features added to SDRAMs original features. If SDF is tied to low, graphic functions are disabled and chip operates
Write Per Bit Enable
Write Per Bit Disable
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Active Power Down Entry
Active Power Down Exit
(9)
V = Valid, X = Don’t Care, H = Logic High, L = Logic Low
OP Code: Operand Code; A0-A10: Program keys (@MRS); A5, A6: LMR or LCR select. (@SMRS) Color register exists only
one per DQi which both banks share. So does Mask Register. Color or mask is loaded into chip through DQ pin.
MRS can be issued only at both banks precharge state. SMRS can be issued only if DQs are idle. A new command can be
issued at the next clock of MRS/SMRS.
Auto refresh functions as same as CBR refresh of DRAM. The automatical precharge without row precharge command is
meant by “Auto”. Auto/Self refresh can be issued only at both precharge state.
A10: bank select address. If “Low” at read, (block) write, row active and precharge, bank A is selected. If “High” at read,
(block) write, row active and precharge, bank B is selected. If A9 is “High” at row precharge, A10 is ignored and both banks
are precharged.
It is determined at row active cycle whether normal/block write operates in write per bit mode or not. For A bank write, at A
bank row active, for B bank write, at B bank row active. Terminology: Write per bit = I/O mask. (Block) Write with write per bit
mode = masked (block) write.
During burst read or write with auto precharge, new read/(block) write command cannot be issued. Another bank read/(block)
write command can be issued at t
Burst stop command is valid only at full page burst length.
DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (write DQM latency is 0) but makes Hi-Z
state the data-out of 2 CLK cycles after. (Read DQM latency is 2.)
as a 16M SDRAM with 32 DQs.
(8)
(4)
(4)
(2,3)
(4)
(5,6,10)
(5,6)
(5,6)
(5,6,7,10)
(5,6,7,10)
(2,3,8)
(5)
(5,6)
(5,6)
CKEn-1
RP
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
after the end of burst.
CKEn
X
X
H
H
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
X
X
X
L
L
L
L
L
CS CS CS CS CS
H
H
X
H
H
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
RAS
RAS
RAS
RAS
H
X
H
H
H
H
H
H
H
H
X
X
H
X
V
X
X
H
X
L
L
L
L
L
L
L
L
CAS
CAS
CAS
CAS
CAS
H
H
H
H
H
H
H
H
H
L
L
L
L
X
L
L
L
L
L
L
X
X
X
V
X
X
X
WE WE WE WE WE
H
H
H
H
H
H
H
H
H
H
L
L
X
L
L
L
L
L
L
L
X
X
X
V
X
X
X
Integrated Silicon Solution, Inc.
DSF
H
X
X
H
H
H
X
X
X
X
X
V
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
ADVANCE INFORMATION SR037-0C
DQM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
X
X
A10
X
X
X
X
V
V
V
V
V
V
V
V
X
V
X
X
X
X
X
X
X
X
X
X
X
OP CODE
OP CODE
A9 A8-A0
X
X
X
X
H Column
H Column
H Column
X
H
X
X
X
X
X
X
X
X
X
X
L
L
L
L
ISSI
Address
Address
Address
Address
Address
Address
Address
Address
Column
Column
Column
09/10/98
Row
Row
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
®