is42g32256 ETC-unknow, is42g32256 Datasheet - Page 35

• Manufacturer Part Number: is42g32256
• Description: 256k 16-mbit Synchronous Graphics
• Manufacturer: ETC-unknow

IS42G32256
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
09/10/98
Figure 19. Single Bit Read-Write-Read Cycle (Same Page) at
Notes:
1. All inputs can be “Don’t Care” when
2. Bank active and read/write are controlled by A10.
3. Enable and disable auto precharge function are controlled by A9 in read/write command.
4. A9 and A10 control bank precharge when precharge command is asserted.
5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command.
6. Block write/normal write is controlled by DSF.
DSF
A10
A10
A9
A9
H
0
1
0
0
1
1
0
0
1
0
0
1
1
L
DSF
A10
A10
Normal write
X
H
H
0
1
0
1
0
1
L
L
Block write
Active and Read/Write
Operation
Bank A
Bank B
Operation
Disable auto precharge, leave bank A active at end of burst.
Disable auto precharge, leave bank B active at end of burst.
Enable auto precharge, precharge bank A at end of burst.
Enable auto precharge, precharge bank B at end of burst.
Precharge
Bank A
Bank B
Both Bank
Operation
Bank A row active, disable write per bit function for bank A.
Bank A row active, enable write per bit function for bank A.
Bank B row active, disable write per bit function for bank B.
Bank B row active, enable write per bit function for bank B.
Minimum cycle time
CS
is high at the CLK high going edge.
t
t
BWC
CCD
CAS
CAS
CAS
CAS
CAS
Latency = 3, Burst Length = 1 (continued)
ISSI
35
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